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25th DSD 2022: Maspalomas, Spain
- 25th Euromicro Conference on Digital System Design, DSD 2022, Maspalomas, Spain, August 31 - Sept. 2, 2022. IEEE 2022, ISBN 978-1-6654-7404-7
- Martin Schoeberl:
Keynote Speakers. xxxvii-xl - Himar Fabelo
, Samuel Ortega:
Message from the Program Chairs: DSD 2022. xxiii-xxiv - Gustavo M. Callicó
Message from the General Chair DSD 2022. 1 - Cherinet Kejela, Rajesh Devaraj, Arnab Sarkar, Sangeet Saha:
A Supervisory Control Approach for Scheduling Real-time Periodic Tasks on Dynamically Reconfigurable Platforms. 1-8 - Minxuan Kong, Kris Nikov
Evaluation of Early-exit Strategies in Low-cost FPGA-based Binarized Neural Networks. 1-8 - Ahsan Javed Awan
Towards Hardware Support for FPGA Resource Elasticity. 9-15 - Kaan Olgu
Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications. 16-23 - Tobias Scheipel
moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems. 24-31 - Salar Hashemi, Amir M. Hajisadeghi
EARL: An Efficient Approximate HaRdware Framework for AcceLerating Fault Tree Analysis. 32-38 - Omkar G. Ratnaparkhi, Madhav Rao:
ESAS: Exponent Series based Approximate Square Root Design. 39-45 - Nima Amirafshar, Ahmad Sadigh Baroughi
An Approximate Carry Disregard Multiplier with Improved Mean Relative Error Distance and Probability of Correctness. 46-52 - Behnam Ghavami, Mahdi Sajedi, Mohsen Raji, Zhenman Fang, Lesley Shannon:
A Majority-based Approximate Adder for FPGAs. 53-59 - Ahmad Sadigh Baroughi
AxE: An Approximate-Exact Multi-Processor System-on-Chip Platform. 60-66 - Abdul Khader Thalakkattu Moosa, Nilotpola Sarma, Chandan Karfa:
ImageSpec: Efficient High-Level Synthesis of Image Processing Applications. 67-74 - Ramakant Joshi, Kuruvilla Varghese:
High-Level Synthesis of Geant4 Particle Transport Application for FPGA. 75-83 - Viktor Herrmann, Justin Knapheide, Fritjof Steinert
A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest Detection. 84-92 - Akshat Ramachandran
PositIV: A Configurable Posit Processor Architecture for Image and Video Processing. 93-100 - Zijie Wang, Jiajun Lu, José L. Núñez-Yáñez:
A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union Launcher. 101-108 - Adnan Ghaderi, Carl Ahlberg, Magnus Östgren, Fredrik Ekstrand, Mikael Ekström:
FP-SLIC: A Fully-Pipelined FPGA Implementation of Superpixel Image Segmentation. 109-117 - Fabio Arnez
Skeptical Dynamic Dependability Management for Automated Systems. 118-125 - Oguz Meteer
Energy-Efficient Radix-4 Belief Propagation Polar Code Decoding Using an Efficient Sign-Magnitude Adder and Clock Gating. 126-133 - Sallar Ahmadi-Pour
Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study. 134-141 - Lukas Jünger, Simon Winther, Rainer Leupers:
X-on-X: Distributed Parallel Virtual Platforms for Heterogeneous Systems. 142-148 - Daniel Casini, Alessandro Biondi
Placement of Chains of Real-Time Tasks on Heterogeneous Platforms under EDF Scheduling. 149-156 - Kanishkan Vadivel, Barry de Bruin
Prebypass: Software Register File Bypassing for Reduced Interconnection Architectures. 157-164 - Viktor Teren
Decomposition of transition systems into sets of synchronizing Free-choice Petri Nets. 165-173 - Nidhi Anantharajaiah, Jürgen Becker:
Adaptive Exploration Based Routing for Spatial Isolation in Mixed Criticality Systems. 174-180 - Mohammad Bawatna, Behnaz Ranjbar
A Hybrid Scheduling Mechanism for Multi-programming in Mixed-Criticality Systems. 181-188 - Timo Sandmann, Jürgen Becker:
Hardware Support for Predictable Resource Sharing in Virtualized Heterogeneous Multicores. 189-196 - Isma-Ilou Sadou, Seyed Morteza Nabavinejad, Zhonghai Lu, Masoumeh Ebrahimi:
Inference Time Reduction of Deep Neural Networks on Embedded Devices: A Case Study. 205-213 - Amritha Immaneni, Salim Ullah
PosAx-O: Exploring Operator-level Approximations for Posit Arithmetic in Embedded AI/ML. 214-223 - Cem Caglayan, Arda Yurdakul:
A Clustering-Based Scoring Mechanism for Malicious Model Detection in Federated Learning. 224-231 - Antti Nurmi
A Resilient System Design to Boot a RISC-V MPSoC. 232-238 - Anu Verma, Priyamvada Sharma, Bishnu Prasad Das:
RISC-V Core with Approximate Multiplier for Error-Tolerant Applications. 239-246 - Johannes Knödtel, Sebastian Rachuj, Marc Reichenbach:
Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the best? 247-253 - Víctor Soria Pardos
Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI. 254-261 - Erdem Derebasoglu, Ismail Kadayif, Ozcan Ozturk:
Coherency Traffic Reduction in Manycore Systems. 262-267 - Pakon Thuphairo, Christopher Bailey, Anthony Moulds, Jim Austin:
Investigating Novel 3D Modular Schemes for Large Array Topologies: Power Modeling and Prototype Feasibility. 268-275 - Antti Rautakoura
Ballast: Implementation of a Large MP-SoC on 22nm ASIC Technology. 276-283 - Marcin Kowalczyk
Hardware architecture for high throughput event visual data filtering with matrix of IIR filters algorithm. 284-291 - Martin Schoeberl
Open-Source Research on Time-predictable Computer Architecture. 292-297 - Yang Hu, Connor Imes, Xuanang Zhao, Souvik Kundu, Peter A. Beerel
PipeEdge: Pipeline Parallelism for Large-Scale Model Inference on Heterogeneous Edge Devices. 298-307 - Joydeep Dey, Sudeep Pasricha:
Co-Optimizing Sensing and Deep Machine Learning in Automotive Cyber-Physical Systems. 308-315 - Veerendra S. Devaraddi, Nanditha P. Rao:
An FPGA based Tiled Systolic Array Generator to Accelerate CNNs. 316-323 - Ehsan Aghapour, Dolly Sapra
CPU-GPU Layer-Switched Low Latency CNN Inference. 324-331 - Atousa Jafari, Mahta Mayahinia, Soyed Tuhin Ahmed
MVSTT: A Multi-Value Computation-in-Memory based on Spin-Transfer Torque Memories. 332-339 - Nandish Chattopadhyay, Rajan Kataria, Anupam Chattopadhyay:
TextBack: Watermarking Text Classifiers using Backdooring. 340-347 - Changjae Yi, Donghyun Kang, Soonhoi Ha:
Hardware-Software Codesign of a CNN Accelerator. 348-356 - Rafael Billig Tonetto, Antonio Carlos Schneider Beck, Gabriel L. Nazar:
SNAP: Selective NTV Heterogeneous Architectures for Power-Efficient Edge Computing. 357-364 - Christoph Gerum, Adrian Frischknecht, Tobias Hald, Paul Palomero Bernardo, Konstantin Lübeck, Oliver Bringmann:
Hardware Accelerator and Neural Network Co-Optimization for Ultra-Low-Power Audio Processing Devices. 365-369 - Floran de Putter, Henk Corporaal:
Quantization: how far should we go? 373-382 - Ihsen Alouani
Breaking (and Fixing) Channel-based Cryptographic Key Generation: A Machine Learning Approach. 383-390 - Hadjer Benmeziane
CaW-NAS: Compression Aware Neural Architecture Search. 391-397 - Halima Bouzidi
Co-Optimization of DNN and Hardware Configurations on Edge GPUs. 398-405 - Gerlando Sciangula, Francesco Restuccia, Alessandro Biondi
Hardware Acceleration of Deep Neural Networks for Autonomous Driving on FPGA-based SoC. 406-414 - Zeqi Zhu, Arash Pourtaherian, Luc Waeijen, Lennart Bamberg, Egor Bondarev, Orlando Moreira:
ARTS: An adaptive regularization training schedule for activation sparsity exploration. 415-422 - Grace Li Zhang
RRAM-based Neuromorphic Computing: Data Representation, Architecture, Logic, and Programming. 423-428 - Martin Roa Villescas
Partial Evaluation in Junction Trees. 429-437 - Sherif Eissa, Sander Stuijk
DNAsim: Evaluation Framework for Digital Neuromorphic Architectures. 438-445 - Paul Delestrac
Demystifying the TensorFlow Eager Execution of Deep Learning Inference on a CPU-GPU Tandem. 446-455 - Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud
A CFI Verification System based on the RISC-V Instruction Trace Encoder. 456-463 - Ihab Alshaer, Brice Colombier, Christophe Deleuze, Vincent Beroulle, Paolo Maistri:
Variable-Length Instruction Set: Feature or Bug? 464-471 - Julien Maillard, Thomas Hiscock, Maxime Lecomte, Christophe Clavier:
Towards Fine-grained Side-Channel Instruction Disassembly on a System-on-Chip. 472-479 - Kai Lehniger, Mario Schölzel, Jonas Jelonek
Combination of ROP Defense Mechanisms for Better Safety and Security in Embedded Systems. 480-487 - Ruize Wang, Kalle Ngo, Elena Dubrova:
Side-Channel Analysis of Saber KEM Using Amplitude-Modulated EM Emanations. 488-495 - Julien Béguinot, Wei Cheng, Sylvain Guilley, Olivier Rioul:
Be My Guess: Guessing Entropy vs. Success Rate for Evaluating Side-Channel Attacks of Secure Chips. 496-503 - Johanna Baehr, Alexander Hepp, Michaela Brunner, Maja Malenko, Georg Sigl:
Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis. 504-512 - Tomás Preucil, Petr Socha, Martin Novotný:
Implementation of the Rainbow signature scheme on SoC FPGA. 513-519 - Nicolas Bordes, Paolo Maistri:
Electromagnetic Leakage Assessment of a Proven Higher-Order Masking of AES S-Box. 520-527 - Yuma Itabashi, Rei Ueno, Naofumi Homma:
Efficient Modular Polynomial Multiplier for NTT Accelerator of Crystals-Kyber. 528-533 - Licinius Benea
On the Characterization of Jitter in Ring Oscillators using Allan variance for True Random Number Generator Applications. 534-538 - Andrea Galimberti
FPGA implementation of BIKE for quantum-resistant TLS. 539-547 - Parangat Sud, Shekoufeh Neisarian
Evaluating Cryptographic Extensions On A RISC-V Simulation Environment. 548-555 - Gaëtan Leplus, Olivier Savry, Lilian Bossuet:
SecDec: Secure Decode Stage thanks to masking of instructions with the generated signals. 556-563 - Paolo Amato, Niccolò Izzo, Carlo Meijer:
Mobile Systems Secure State Management. 564-571 - Mireia Perera-Gonzalez, Kristine Y. Ma, Chris A. Flask
In vitro Testbed Platform for Evaluating Small Volume Contrast Agents via Magnetic Resonance Imaging. 572-576 - Floran de Putter, Maurice Peemen, Pavel Potocek, Remco Schoenmakers, Henk Corporaal:
CELR: Cloud Enhanced Local Reconstruction from low-dose sparse Scanning Electron Microscopy images. 577-584 - Christos Goumopoulos, Damianos Ougkrenidis, Dimitris Gklavakis, Iraklis Ioannidis:
A Smart Floor Device of an Exergame Platform for Elderly Fall Prevention: *Note: Sub-titles are not captured in Xplore and should not be used. 585-592 - Alexandre Bordat, Petr Dobiás, Julien Le Kernec, David Guyard, Olivier Romain:
GPU Based Implementation for the Pre-Processing of Radar-Based Human Activity Recognition. 593-598 - Najma Taimoor, Semeen Rehman:
On the Validation of Multi-Level Personalised Health Condition Model. 599-606 - María Castro-Fernández
Towards Skin Cancer Self-Monitoring through an Optimized MobileNet with Coordinate Attention. 607-614 - Christian Lienen, Marco Platzner:
Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications. 615-623 - Benoit Varillon, David Doose:
Real-Time Polling Task: Design and Analysis. 624-631 - Marius Herget
Design Space Exploration for Distributed Cyber-Physical Systems: State-of-the-art, Challenges, and Directions. 632-640 - David Haunschmied, Udo Kannengiesser:
How are Industry 4.0 Reference Architectures Used in CPPS Development? 641-648 - Gautam Gala
Monitoring Framework to Support Mixed-Criticality Applications on Multicore Platforms. 649-656 - Zaheer Tabassam, Andreas Steininger
Towards Resilient QDI Pipeline Implementations. 657-664 - Ondrej Novák:
Nonlinear Compression Block Codes Search Strategy. 665-670 - Mohammad Reza Heidari Iman, Jaan Raik, Gert Jervan, Tara Ghasempouri
IMMizer: An Innovative Cost-Effective Method for Minimizing Assertion Sets. 671-678 - Leandro Batista Ribeiro, Drona Nagarajan, Vignesh Manjunath, Muhammad Tanveer Ali Ahmad, Marcel Baunach:
Verifying Liveness and Real-Time of OS-Based Embedded Software. 679-688 - Jan Reznícek, Martin Kohlík, Hana Kubátová:
Verification of Calculations of Non-Homogeneous Markov Chains Using Monte Carlo Simulation. 689-695 - Juliano Pimentel, Alistair A. McEwan, Hong Qing Yu:
Towards a Real-Time Smart Prognostics and Health Management (PHM) of Safety Critical Embedded Systems. 696-703 - Fabian Kempf, Christoph Kühbacher, Christian Mellwig, Sebastian Altmeyer, Theo Ungerer, Jürgen Becker:
A holistic hardware-software approach for fault-aware embedded systems. 704-711 - Andrea Biagioni, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci
RED-SEA: Network Solution for Exascale Architectures. 712-719 - Antonio J. Sánchez
Abeto framework: a Solution for Heterogeneous IP Management. 720-725 - Norbert Druml, Philipp Greiner, Ievgeniia Maksymova, Leonhard Christian Niedermueller:
Sense and Control of Oscillating MEMS Mirrors. 726-732 - Réda Nouacer, Raphaël Lallement, Rodrigo Castiñeira, Jean-Frédéric Real, Jean-Patrick Mascomère:
COMP4DRONES: Key Enabling Technologies for Drones to enhance Mobility and Logistics Operations. 733-740 - Federica Caruso, Tania Di Mascio
Sentient Spaces: Intelligent Totem Use Case in the ECSEL FRACTAL Project. 741-747 - Nicolas Sklavos
Network on Privacy-Aware Audio-and Video-Based Applications for Active and Assisted Living: GoodBrother Project. 748-753 - Mehrdad Saadatmand, Eduard Paul Enoiu, Holger Schlingloff, Michael Felderer, Wasif Afzal:
SmartDelta: Automated Quality Assurance and Optimization in Incremental Industrial Software Systems Development. 754-760 - Martha Schnieber, Saman Fröhlich, Rolf Drechsler
Polynomial Formal Verification of Approximate Adders. 761-768 - Abhoy Kole, Kamalika Datta, Indranil Sengupta, Rolf Drechsler
SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library. 769-776 - Andrea Guerrieri
Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis. 777-784 - Milan Ceska, Jirí Matyás, Vojtech Mrazek, Tomás Vojnar:
Designing Approximate Arithmetic Circuits with Combined Error Constraints. 785-792 - Kamalika Datta, Saeideh Shirinzadeh, Phrangboklang Lyngton Thangkhiew, Indranil Sengupta, Rolf Drechsler
Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles. 793-800 - Richard Ruzicka, Václav Simek:
Technology Mapping for PAIG Optimised Polymorphic Circuits. 801-808 - Debraj Kundu, Sudip Roy:
MEDA Biochip based Single- Target Fluidic Mixture Preparation with Minimum Wastage. 809-814 - Saman Fröhlich, Rolf Drechsler
Generation of Verified Programs for In-Memory Computing. 815-820 - Saeed Seyedfaraji
SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS Technology. 821-826 - Anna Schröder, Marianne Maktabi
Evaluation of artificial neural networks for the detection of esophagus tumor cells in microscopic hyperspectral images. 827-834 - Alberto Martín-Pérez
Hyperparameter Optimization for Brain Tumor Classification with Hyperspectral Images. 835-842 - Juan N. Mendoza-Chavarría, Eric R. Zavala-Sánchez, Liliana Granados-Castro
Glioblastoma Classification in Hyperspectral Images by Nonlinear Unmixing. 843-848 - Liliana Granados-Castro
Estimation of deoxygenated and oxygenated hemoglobin by multispectral blind linear unmixing. 849-854 - Inés A. Cruz-Guerrero
Reflectance Calibration with Normalization Correction in Hyperspectral Imaging. 855-862 - Carlos Vega
Development of a Hyperspectral Colposcope for Early Detection and Assessment of Cervical Dysplasia. 863-870 - Marco La Salvia, Emanuele Torti, Marco Gazzoni, Elisa Marenzi
Attention-based Skin Cancer Classification Through Hyperspectral Imaging. 871-876 - Ludovica Adacher, Marta Flamini:
A resolution method in case of air congestion: rerouting and/or ground holding approach. 877-884 - Theodoros Karachalios, Christos Xouris, Theofanis Orphanoudakis:
Optimizing UAV location awareness telemetry data for Low Power Wide Area Network. 885-888 - Sathwika Bavikadi
POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications. 889-898 - Behnam Ghavami, Mani Sadati, Mohammad Shahidzadeh, Zhenman Fang, Lesley Shannon:
Blind Data Adversarial Bit-flip Attack against Deep Neural Networks. 899-904 - Dominik Marchsreiter, Johanna Sepúlveda:
Hybrid Post-Quantum Enhanced TLS 1.3 on Embedded Devices. 905-912 - Ipsita Koley, Sunandan Adhikary, Rohit Rohit, Soumyajit Dey:
A Framework for Evaluating Connected Vehicle Security against False Data Injection Attacks. 913-920 - Soumyadyuti Ghosh, Urbi Chatterjee, Soumyajit Dey, Debdeep Mukhopadhyay:
Is the Whole lesser than its Parts? Breaking an Aggregation based Privacy aware Metering Algorithm. 921-929
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