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ECCTD 2005: Cork, Ireland
- Proceedings of the 2005 European Conference on Circuit Theory and Design, ECCTD 2005, Cork, Ireland, August 29th - September 1st 2005. IEEE 2005, ISBN 0-7803-9066-0
Volume 1
- Giovanni De Micheli:
Plenary lecture [Second page is blank]. 1-2 - Kuniyasu Shimizu, Tetsuro Endo:
Stability of the quasi-periodic and periodic attractors constrained to the hyper-plane in a ring of three-coupled hard-type oscillators. 3-6 - Takuji Kousaka, Yue Ma:
Bifurcation analysis in a hybrid time delay system. 7-10 - Tomoumi Yagasaki, Yoshihiko Horio, Kazuyuki Aihara:
One-dimensional discrete-time dynamical systems circuit using floating-gate MOS peaking current sink/source. 11-14 - Markku Åberg, Jan Saijets:
DC and AC characteristics and modeling of Si SSD-nano devices. 15-18 - Sebastian Prot, Mark F. Flanagan
, Conor Heneghan:
Conditional quasi maximum-likelihood receiver for clipped OFDM signals. 19-22 - Luís Nero Alves
On the usage of delayed-feedback in amplifiers. 23-26 - Raimondo Luzzi, Salvatore Pennisi
2-V CMOS current operational amplifier with high CMRR. 27-30 - Nobukazu Takai, Shinji Nomura:
Rail-to-rail OTA utilizing linear V-I conversion circuit using single channel MOSFETs for input stage. 31-34 - Belén Calvo, Santiago Celma, Pedro A. Martínez, Maria Teresa Sanz
1.8 V.0.35 μm CMOS wideband programmable gain amplifier. 35-38 - Alkis A. Hatzopoulos
Analysis of coil parameter extraction methods for on-chip inductor design. 39-42 - Jacek Izydorczyk:
Simulation of ferrites by SPICE. 43-46 - Timo Veijola:
Compact model for a cantilever beam MEM contact switch. 47-50 - Caroline Lelandais-Perrault, Daniel Poulton, Jacques Oksman:
Band-pass hybrid filter bank A/D converters with software-controlled bandwidth and resolution. 51-54 - K. Ola Andersson, Mark Vesterbacka:
A yield-enhancement strategy for binary-weighted DACs. 55-58 - Jeffrey O. Coleman:
Modeling finite-memory nonlinearity in unit DAC elements, binary storage channels, and BPSK data channels. 59-62 - Chatree Budsabathon, Akinori Nishihara:
Dithered subband coding with spectral subtraction. 63-66 - Mark F. Flanagan, Anthony D. Fagan:
A Gradient-based adaptive algorithm for minimum phase-all pass decomposition of an FIR system. 67-70 - Naomi Harte
Towards a hardware realization of time-frequency source separation of speech. 71-74 - Fausto Sargeni
Time division digital programmable OTA for cellular neural networks. 75-78 - Péter Sonkoly, Sándor Kocsárdi, Péter Kozma, Péter Szolgay:
Inverse elastic wave propagation modeling on CNN-UM architecture. 79-82 - Mario Salerno, Daniele Casali, Giovanni Costantini
A customizable tool for cellular nonlinear network simulation. 83-86 - Shadi Tawfik, Tian Tong, Troels Studsgaard Nielsen, Torben Larsen:
A 1.9 GHz CMOS class E power amplifier with +29 dBm output power and 58% PAE. 87-90 - Shashikanth Bobba, Ashoka S. V., Thomas Mattsson, Stefan Nilsson:
Design of a novel type of on-chip transformer suitable for baluns in customary BICMOS/CMOS technologies. 91-94 - Ali Fard, Denny Åberg:
A reconfigurable CMOS VCO with an automatic amplitude controller for multi-band RF front-ends. 95-98 - Mikko Loikkanen, Juha Kostamovaara:
Improving capacitive drive capability of two-stage op amps with current buffer. 99-102 - Emanuele Bottino, Maurizio Valle
Integrated low noise preamplifier for biologic-electronics interfaces. 103-106 - Andrzej Handkiewicz, Radoslaw Rudnicki, Marek Kropidlowski:
Switched current filter design with the use of integrators composed of equal size transistors. 107-110 - William Prodanov, Maurizio Valle
A behavioral model for the nonlinear on-resistance in sample-and-hold analog switches. 111-114 - M. Helena Fino:
A simple submicron MOSFET model and its application to the analytical characterization of analog circuits. 115-118 - Juan Pablo Alegre, Santiago Celma, Maria Teresa Sanz
Comparative study of MOST resistive configurations. 119-122 - Yujin Park, Sanghoon Hwang, Minkyu Song:
An interpolated flash type 6-b CMOS A/D converter with a DC reference fluctuation reduction technique. 123-126 - Erik Säll, Mark Vesterbacka:
6 bit 1 GHz CMOS silicon-on-insulator flash analog-to-digital converter for read channel applications. 127-130 - Sunghyun Park, Michael P. Flynn:
Design techniques for high performance CMOS flash analog-to-digital converters. 131-134 - Joachim F. Selinger, Axel Wenzler:
Robust reconstruction of nonuniformly sampled signals. 135-138 - Lars Wanhammar, Kenny Johansson, Oscar Gustafsson
Efficient sine and cosine computation using a weighted sum of bit-products. 139-142 - Fredrik Edman, Viktor Öwall:
Fixed-point implementation of a robust complex valued divider architecture. 143-146 - Ivo Bolsens:
Plenary lecture [Second page is blank]. 147-148 - Víctor M. Brea
Robustness improvement in binary cellular non-linear network architectures. 149-152 - Xavier Vilasís-Cardona, Mireia Vinyoles-Serra:
On cellular neural network learning. 153-156 - Ahmed Ayoub, Szabolcs Tõkés:
A new CNN template for POAC peak enhancement. 157-160 - Lasse Aaltonen, Mikko Saukoski, Kari Halonen:
Design of clock generating fully integrated PLL using low frequency reference signal. 161-164 - Luca Antonio De Michele, Fabio Pareschi
Chaos-based high-EMC spread-spectrum clock generator. 165-168 - Andreas Mögel, Jörg Krupar, Wolfgang M. Schwarz:
EMI performance of spread spectrum clock signals with respect to the IF bandwidth of the EMC standard. 169-172 - Joe C. P. Liu, Chi K. Tse, Franki N. K. Poon, M. H. Pong, William Y. M. Lai
General impedance synthesizer using minimal configuration of switching converters. 173-176 - Octavian Dranga, Chi K. Tse, Siu Chung Wong
Stability analysis of complete two-stage power-factor-correction power supplies. 177-180 - Serhan Yamaçli, Sadri Özcan, Hakan Kuntman:
Resistorless KHN biquad using an DDA (difference diffference amplifier) and two CCCIIs (controlled current conveyor). 181-184 - Marko Neitola
A fully automated flowgraph analysis tool for Matlab. 185-188 - Masaya Yoshikawa, Hidekazu Terai:
Hybrid genetic algorithm engine for high-speed floorplanning. 189-192 - K. L. Man:
SystemCFL: a formalism for hardware/software codesign. 193-196 - Juan M. Carrillo
1.8-V second-order ΣΔ modulator in 0.18-μm CMOS technology. 197-200 - Esmaeil Najafi Aghdam
Higher order dynamic element matching by shortened tree-structure in delta-sigma modulators. 201-204 - Cristina Della Fiore, Franco Maloberti:
Design of ΣΔ modulators with reduced number of operational amplifiers. 205-208 - François-Xavier Coudoux, Marc Gazalet, Patrick Corlay:
A DCT-domain postprocessor for color bleeding removal. 209-212 - Mattias O'Nils, Per-Robert Lilljefjäll, Benny Thörnberg
Data partitioning for parallel implementation of real-time video processing systems. 213-216 - Adam Luczak, Pawel Garstecki:
A flexible architecture for image reconstruction in H.264/AVC decoders. 217-220 - Barry O'Donnell, Paul F. Curran, Orla Feely
On the bifurcation properties of a class of differentiable mappings. 221-224 - Zhong Zhang, Guanrong Chen
Chaotic motion generation with applications to liquid mixing. 225-228 - Yoko Uwate, Yoshifumi Nishio
Modeling using 1-D map of complex behavior in coupled chaotic circuits with intermittency. 229-232 - Emer Condon, Paul F. Curran, Ketan Mistry, Orla Feely:
On the steady state behaviour of an nth-order class of nonlinear mappings. 233-236 - Mikko Hotti, Jussi Ryynänen
RC-load analysis of the downconversion mixer IIP2. 237-240 - Morgan Fitzgibbon, Diarmuid McSwiney, Dermot O'Keeffe, Jyoti Mondal, David Redmond, William Waldie:
A single package transceiver for quad band EGPRS (GSM/GPRS/EDGE) class 12 applications. 241-244 - Aránzazu Otín
Low voltage LC-ladder Gm-C low-pass filters with 42-215 MHz tunable range. 245-248 - Calogero D. Presti, Francesco Carrara, Giuseppe Palmisano:
Variable-gain up-conversion mixer with current reuse for 5-GHz W-LAN applications. 249-252 - Mikko Varonen
Metamorphic HEMT amplifier for K- and Ka-band applications. 253-256 - Pietro Monsurrò
Switched-capacitor body-biasing technique for very low voltage CMOS amplifiers. 257-260 - Juan M. Carrillo
1-V rail-to-rail bulk-driven CMOS OTA with enhanced gain and gain-bandwidth product. 261-264 - Giuseppe Di Cataldo, Salvatore Pennisi
CMOS interface for differential capacitive transducers. 265-268 - Hold Omid Rajaee, Mehrdad Sharif Bakhtiar:
A low voltage, high speed current mode sample and hold for high precision applications. 269-272 - Alfio Dario Grasso
Current-steering D/A converter based on triple tail cell. 273-276 - Francis C. M. Lau, Alan Daly, William P. Marnane
Optimised Montgomery domain inversion on FPGA. 277-280 - Juan Carlos López-García, Marco A. Moreno-Armendáriz
Real time vision by FPGA implemented CNNs. 281-284 - D. Bianchi, Gian Carlo Cardarilli
FPGA implementation of a general purpose HMM processor based on token passing algorithm. 285-288 - Christian Spagnol, William P. Marnane
Reduced complexity, FPGA implementation of quasi-cyclic LDPC decoder. 289-292 - Martin Vogels, Georges G. E. Gielen:
Systematic top-down design of A/D converters. 293-296 - Alessandro Cabrini, Franco Maloberti:
Use of non-linear Chua's circuit for on-line offset calibration of ADC. 297-300 - Stephen O'Driscoll, Teresa H. Meng:
Adaptive ADC design for neuro-prosthetic interfaces: base ADC cell. 301-304 - Marko Kosunen, Kari Halonen:
Sampling jitter and power supply interference in current-steering D/A converters. 305-308 - Carsten Wegener, Michael Peter Kennedy:
Innovation to overcome limitations of test equipment. 309-314 - Iulian B. Ciocoiu
Occluded face recognition using parts-based representation methods. 315-318 - Takenobu Matsuura, Kazuki Izumi:
A realization of FIR system for on-line writer recognition. 319-322 - Shuitsu Matsumura, Tsuyoshi Takebe:
An effective compression scheme for prediction errors on lossless image coding. 323-326 - Sarunas Paulikas, Dalius Navakauskas:
Recognition of isolated words corrupted by impulsive noise. 327-330 - Peter Michael Goebel, Ahmed Nabil Belbachir, Michael Truppe
Background removal in dental panoramic X-ray images by the A-Trous multiresolution transform. 331-334
Volume 2
- Árpád I. Csurgay, Wolfgang Porod, Stephen M. Goodnick:
The circuit paradigm in nanoelectronics - field-coupled and hybrid nanoelectronic circuits. 1-6 - Alon Ascoli, Paul F. Curran, Orla Feely:
A slow-fast dynamics model of a second-order logdomain floating-capacitor LC-ladder circuit. 7-10 - Pedro Ramírez, Andrés Guesalaga:
Non-linear dynamics in servo positioning loops. 11-14 - Seiichiro Moro
On phase pattern transition in star-coupled Wien-bridge oscillators with parameter deviations. 15-18 - Erik Lindberg
Oscillators and operational amplifiers. 19-22 - Ali Banai, Forouhar Farzaneh:
Theoretical investigation of the stability of the modes in an array of coupled oscillators for linear and circular arrangements. 23-26 - John Vosper, Richard Deloughry, Brett Wilson:
Multiphase active-RC sinusoidal oscillators incorporating lowpass and allpass sections. 27-30 - Shingo Takahashi, Akira Taji, Shuji Tsukiyama, Masanori Hashimoto
A design scheme for sampling switch in active matrix LCD. 31-34 - Alessandro Cabrini, Laura Gobbi, Guido Torelli:
A theoretical discussion on performance limits of CMOS charge pumps. 35-38 - Paolo Stefano Crovetti
Nonlinear effects of RF interference in SC circuits. 39-42 - Angelo Brambilla
Partitioning large circuits to speed up numerical simulations. 43-46 - Pedro C. Ventura, Marco Oliveira:
A methodology for fast reuse of analog circuit schematics. 47-50 - Andreas Bauer:
Efficient algorithms for the computation and application of Volterra kernels in the behavior analysis of nonlinear circuits and systems. 51-54 - Olujide A. Adeniran, Andreas Demosthenous:
Optimization of bit-per-stage for low-voltage low-power CMOS pipeline ADCs. 55-58 - José L. Ausín
Linearity enhancement of oversampled pipeline A/D converters using sigma-delta modulation. 59-62 - Takeshi Koike, Akira Hyogo, Keitaro Sekine:
A 2.0-V folding circuit using current limiting amplifier for ADC. 63-66 - Marco Balsi
Constrained ICA for functional magnetic resonance imaging. 67-70 - Ichiro Matsuda, Taichiro Shiodera, Hiroki Maeda, Susumu Itoh:
Lossless video coding using bi-directional 3D prediction optimized for each frame. 71-74 - Krzysztof Slot
Feature space derivation for isolated utterance reading with discriminant deformable models. 75-78 - Géza Kolumbán:
UWB technology: chaotic communications versus noncoherent impulse radio. 79-82 - Keith O'Donoghue, Michael Peter Kennedy, Peadar Forbes:
A fast and simple implementation of Chua's oscillator using a "cubic-like" Chua diode. 83-86 - Piotr Dudek, V. D. Juncu:
An area and power efficient discrete-time chaos generator circuit. 87-90 - Behnam Sedighi, Hold Omid Rajaee, Amin Jahanian, Mehrdad Sharif Bakhtiar:
A 1.5V 150MS/s current-mode sample-and-hold circuit. 91-94 - Behnam Sedighi, Mehrdad Sharif Bakhtiar:
A 1.5V 60MS/s sampled-data filter in 0.18μm CMOS. 95-98 - Davide De Caro
A high-speed sense-amplifier based flip-flop. 99-102 - Antonio J. López-Martín
Design of high-performance tunable filters based on current conveyors. 103-106 - Karel Hajek
Minimization of offset of the tunable LP filters. 107-110 - Klaus Schmalz, Mykhaylo A. Teplechuk, John I. Sewell:
A class AB 6th order log-domain filter in BiCMOS with 100-500 MHz tuning range. 111-114 - David G. Haigh:
Systematic synthesis of operational amplifier circuits by admittance matrix expansion. 115-118 - Engin Deniz, Günhan Dündar
Performance estimator for an analog design automation system using EKV-modeled analog circuits. 119-122 - Mattias O'Nils, Bengt Oelmann, Kent Bertilsson, Hans-Erik Nilsson, Göran Thungström:
A project based master's programme for SoF/SoC based sensor systems. 123-126 - Jaap Hoekstra:
Prediction of Coulomb blockade in arbitrary environments. 127-130 - Nicholas P. Carter, Steve Ferrera, Love Kothari, Stanley Ye:
Hall-effect circuits and architectures for non-volatile system design. 131-134 - Woo Hyung Lee, Pinaki Mazumder:
New logic circuits consisting of quantum dots and CMOS. 135-138 - Yuri Dolgin, Ezra Zeheb:
Computing minimum-phase factors of polynomials. 139-142 - D. Adamidis, Haridimos T. Vergos:
Modulo 2n - 1 multiplication/sum-of-squares units. 143-146 - Corneliu Rusu
Argument principle and discrete Fourier transform. 147-150 - Leon O. Chua:
Plenary lecture [Second page is a blank]. 151-152 - Bartosz Swiderski
Lyapunov exponent of EEG signal for epileptic seizure characterization. 153-156 - Xia Zheng, Francis C. M. Lau
Study of nonlinear dynamics of LDPC decoders. 157-160 - Laurent Larger
Route to chaos in an opto-electronic system. 161-164 - Serdar Özoguz
A non-autonomous IC chaotic oscillator and its application for random bit generation. 165-168 - Michael Small
Chaotic dynamics and simulation of Japanese vowel sounds. 169-172 - Mike Beigel, John McGary:
Accurate, real-time localization of subminiature inductive transponders: tumor localization as an example. 173-176 - Fatih Kocer
A new transponder architecture for long-range telemetry applications. 177-180 - Vojtech Derbek, Josef Preishuber-Pfluegl, Christian Steger, Markus Pistauer:
Architecture for model-based UHF RFID system design verification. 181-184 - Youbok Lee, James Nolan:
Low frequency bidirectional communication transponder for security and automotive applications. 185-188 - Ulrich Kaiser:
UICE: a low-power high-speed cryptographic module for RFID and embedded systems. 189-192 - Ali Tugberk Bekri, Fuat Anday:
Nth-order low-pass filter employing current differencing transconductance amplifiers. 193-196 - Dasa Ticha, Pravoslav Martínek:
OTA-C lowpass design using evolutionary algorithms. 197-200 - Masood ul-Hasan, Yichuang Sun, Yisheng Zhu:
Second-order OTA-C filters using a single OTA. 201-204 - Juan Francisco Fernández-Bootello, Manuel Delgado-Restituto
Dynamic range optimization of continuous-time Gm-C filters. 205-208 - Antonio J. López-Martín
A 70dB SFDR CMOS transconductor. 209-212 - Julian P. Murphy, Alex Yakovlev
Power-balanced asynchronous logic. 213-216 - Vijayakumar Kalyanaraman, Matthias Müller, Sven Simon, Mario Steinert, Holger Gryska:
A power dissipation comparison of ALU-architectures for ASIPs. 217-220 - Eduardo A. C. da Costa
Maximal sharing of partial terms in MCM under minimal signed digit representation. 221-224 - Mehmet Sagbas, Muhammet Köksal:
A new multi-mode multifunction filter using CDBA. 225-228 - Frank Felgenhauer, M. Begoin, Wolfgang Mathis
Q-parasitics and their influence to the behaviour of nanoscaled CMOS circuits. 229-232 - Pier Paolo Civalleri, Marco Gilli, Michele Bonnin
Circuit models for small signal performance of nanodevices based on two-state quantum systems. 233-236 - Konstantin K. Likharev:
CMOL: possible hybrid semiconductor/nanodevice circuits. 237-238 - Luca Bonci, Massimo Macucci
Numerical investigation of energy dissipation in Quantum Cellular Automaton circuits. 239-242 - Han-Wei Wang, I-Ming Tsai, Chih-Neng Chung, Sy-Yen Kuo
A scheme to enhance the error-correcting capability of encoded quantum information. 243-246 - Olli Väänänen, Mikko Kaltiokallio, Jouko Vankka, Kari Halonen:
A method for compensating the D/A converter frequency response distortion in OFDM system. 247-250 - Pawel Turcza, Tomasz Twardowski:
RLS based MIMO channel identification for FEXT compensation in vectored xDSL system. 251-254 - Tomasz Twardowski, Tomasz P. Zielinski
Equalizer design for discrete multitone systems combining response shortening and spectral shaping. 255-258 - Emanuele Lopelli, Johan van der Tang, Arthur H. M. van Roermund:
A FSK demodulator comparison for ultra-low power, low data-rate wireless links in ISM bands. 259-262 - Sanjit K. Mitra, Mikhail K. Tchobanou, Mikhail I. Bryukhanov:
A general method for designing sparse antenna arrays. 263-266
Volume 3
- Alfred Fettweis:
Plenary lecture [Second page is a blank]. 1-2 - Ganesh Kumar Basnet, Masayuki Yamauchi, Mamoru Tanaka:
Neural network simulator for circuit modeling and analysis based on fast automatic differentiation. 3-6 - Norikazu Takahashi, Tsuyoshi Yamakawa, Tetsuo Nishi:
Realization of limit cycles by neural networks with piecewise linear activation function. 7-10 - Jasper Stolte, György Cserey:
Artificial immune systems based sound event detection with CNN-UM. 11-14 - Iasonas F. Triantis
An improved, very long time-constant CMOS integrator for use in implantable neuroprosthetic devices. 15-18 - Xiao Liu, Andreas Demosthenous:
Generation of balanced biphasic stimulus current with integrated blocking capacitor. 19-22 - Paul Annus
Design of a bioimpedance measurement system using direct carrier compensation. 23-26 - Giuseppe Ferri
A novel CMOS temperature control system for resistive gas sensor arrays. 27-32 - Mattia Malfatti, Matteo Perenzoni
A complete front-end system read-out and temperature control for resistive gas sensor array. 31-34 - John Barton, Brendan O'Flynn
A miniaturised modular platform for wireless sensor networks. 35-38 - Michal Tadeusiewicz
Analysis of diode-transistor circuits having multiple DC solutions. 39-42 - David G. Haigh, Paul M. Radmore:
New admittance matrix descriptions for the nullor with application to circuit design. 43-46 - Martin Claus:
Geometrical analysis of two-transistor circuits with more than three operating points. 47-50 - Abdelali El Aroudi, Roberto Giral
Novel autonomous current mode one-cycle controller for PFC AC-DC pre-regulators. 51-54 - Abdelali El Aroudi, Bruno Robert
Sliding mode control of a high voltage DC-DC buck converter. 55-60 - Krzysztof Siwek
Blind source separation for improved load forecasting in the power system. 61-64 - John W. Nieto:
An investigation of coded OFDM and OFDM-CDMA waveforms utilizing different modulation schemes on HF multipath/fading channels. 65-68 - Mikko Talonen, Saska Lindfors:
System requirements for OFDM polar transmitter. 69-72 - Tetsuya Shimamura, Takeshi Tomikura:
Quality improvement of bone-conducted speech. 73-76 - Giovanni Egidio Pazienza, Pasqualino Giangrossi, Sebastià Tortella, Marco Balsi
Tracking for a CNN guided robot. 77-80 - Aliaksei Lopich, Piotr Dudek:
Architecture of asynchronous cellular processor array for image skeletonization. 81-84 - Taisuke Nishio, Yoshifumi Nishio
Image processing using periodic pattern formation in cellular neural networks. 85-88 - Janne P. Aikio
Reliability of polynomial IDS-VGS-VDS model fitted using harmonic-balance simulation. 89-92 - Salvatore Omar Cannizzaro, Gaetano Palumbo, Salvatore Pennisi
Distortion analysis of three-stage amplifiers with reversed nested-Miller compensation. 93-96 - Salvatore Omar Cannizzaro, Gaetano Palumbo, Salvatore Pennisi
New analytical approach to evaluate harmonic distortion in nonlinear feedback amplifiers. 97-100 - Dusan M. Milosevic, Johan van der Tang, Arthur H. M. van Roermund:
Explicit design equations for class-E power amplifiers with small DC-feed inductance. 101-104 - Hiroo Sekiya
Design of class E amplifier with any output Q and nonlinear capacitance on MOSFET. 105-108 - Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo:
Guidelines for designing class-AB output stages. 109-112 - Mohammad Hadi Eghlidi, Khashayar Mehrany, Bizhan Rashidian:
General solution of linear differential equations by using differential transfer matrix method. 113-116 - Marian S. Piekarski, Robert T. Wirski
On the transfer matrix synthesis of two-dimensional orthogonal systems. 117-120 - Mark M. Gourary, Sergey G. Rusakov
Frequency adjusting numerical technique for oscillator simulation. 121-124 - Juliusz Modzelewski, Miroslaw Mikolajewski
Output power control in a power combiner with class-DE amplifiers. 125-128 - Hao Zhang
Study of parasitic and stray components induced ringings in class E power amplifiers in MHz range. 129-132 - Yuichi Tanji, Hiroo Sekiya
Optimization procedure of class E amplifiers using SPICE. 133-136 - Dora Lee, Wai Tung Ng:
Beamforming system for 3G and 4G wireless LAN applications. 137-140 - Flavio Carbognani, Felix Bürgin, Luca Henzen, Herbert Koch, Hovig Magdassian, Christoph Pedretti, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
A 0.67-mm2 45-μW DSP VLSI implementation of an adaptive directional microphone for hearing aids. 141-144 - Byungjin Chun:
A downlink beamforming in consideration of common pilot and phase mismatch. 145-148 - Ákos Zarándy, Péter Földesy, Tamás Roska:
Per-pixel integration time controlled image sensor. 149-152 - Asko Kananen, Ari Paasio
A simple variable λ resistive network implementation. 153-156 - Kazuya Tsuruta, Yoshifumi Nishio
Reversible watermarking technique using small-world cellular neural network. 157-160 - Hisashi Aomori, Tsuyoshi Otake, Nobuaki Takahashi, Mamoru Tanaka:
Hybrid lifting scheme using discrete-time cellular neural networks for lossless image coding. 161-164 - Daniele Casali, Giovanni Costantini
A cellular neural network based character recognition system. 165-168 - Andrea Anzalone, Federico Bizzarri
A CNN for biomedical image processing. 169-172 - Stefano Santi, Matias Ballardini, Riccardo Rovatti
The effects of digital implementation on ZePoC codec. 173-176 - Troels Studsgaard Nielsen, Saska Lindfors, Torben Larsen:
Simplified workfunction predistorter noise analysis. 177-180 - Behnam Faraji, Mohammad Hadi Eghlidi, Khashayar Mehrany, Bizhan Rashidian:
Analytical approach for analyzing tapered transmission lines. 181-184 - Antonio Buonomo, Alessandro Lo Schiavo:
Modeling and analysis of a relaxation oscillator. 185-188 - Kazuya Yoshizaki, Shigetaka Takagi, Nobuo Fujii:
Phase-error reduction technique for quadrature ring oscillators. 189-192 - Wei-Bin Yang, Shu-Chang Kuo, Yuan-Hua Chu, Kuo-Hsing Cheng:
The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle. 193-196 - Christian Merkwirth, Jörg D. Wichard, Maciej Ogorzalek
A software toolbox for constructing ensembles of heterogenous linear and nonlinear models. 197-200 - Piotr Bilski, Zbigniew Walczak, Jacek Wojciechowski:
Diagnostics of analog systems using rough sets. 201-204 - Michal Tadeusiewicz
Multiple fault diagnosis in analogue circuits. 205-208 - Nikolaos Terzopoulos, Khaled Hayatleh, Bryan L. Hart, F. J. Lidgey:
The collector-base resistance of a BJT. 209-212 - Paula López
Practical considerations on doughnut transistors design. 213-216 - Guillermo Zatorre-Navarro, Nicolás J. Medrano-Marqués, Santiago Celma Pueyo:
A mixed-mode conditioning circuit designed for adaptive smart sensing. 217-220 - Alfio Dario Grasso
Optimized design of ECL gates with a power constraint. 221-224 - Hirofumi Suzuki, Hidemasa Kubota, Takayuki Watanabe, Hideki Asai
Interconnect simulation using FDTD method with variable mesh size technique. 225-228 - Matteo Perenzoni
A systematic design procedure for high-speed opamp performance optimization. 229-232 - Giulio Antonini
Ladder network modeling for closed-form interconnect time delay determination. 233-236 - Conor Buckley, Sverre Lidholm:
Minimising buffer latency through optimum transistor p-to-n ratio scaling. 237-240 - Billy Tomatsopoulos, Andreas Demosthenous:
Low power, low complexity CMOS multiple-input replicating current comparators and WTA/LTA circuits. 241-244 - Alfonso Fernández-Vázquez, Gordana Jovanovic-Dolecek
One method for linear phase lowpass IRR filter design. 245-248 - Krister Landernäs, Johnny Holmberg:
Implementation of high-speed digit-serial LDI allpass filters. 249-252 - Hideaki Sakai:
Exact convergence analysis of adaptive filter algorithms without persistently exciting condition. 253-256 - Rafal Dlugosz, Pawel Pawlowski
Finite impulse response filter banks realized using switched capacitor technique. 257-260 - Goran Molnar, Mladen Vucic:
Time-domain distortion as criterion for design of IIR Hilbert transformers. 261-264 - Lorant Burian, Peter Fuchs:
A simple active noise control in acoustic duct. 265-268 - Andrew Byrne, Emanuel M. Popovici, Michael E. O'Sullivan
Versatile architectures for decoding a class of LDPC codes. 269-272 - Mohsen Nickray, Masoud Dehyadegari
Power and delay optimization for network on chip. 273-276 - Nariman Moezzi Madani, Javad Hadi, Sied Mehdi Fakhraie:
Design and implementation of a fully digital 4FSK demodulator. 277-280 - Mohammad Hajirostam, Ken Martin:
An analog-digital adaptive image-reject technique for quadrature receivers. 281-284 - Anton Blad, Oscar Gustafsson
An early decision decoding algorithm for LDPC codes using dynamic thresholds. 285-288 - Binboga Siddik Yarman
Reflectance data model with mixed lumped and distributed elements for wireless communication systems. 289-292 - Lubomír Brancík
Novel method of sensitivity evaluation in hybrid circuits with nonuniform distributed parts. 293-296 - Thomas Ott, Justin Dauwels, Ruedi Stoop:
Sequential clustering by loopy belief propagation. 297-300 - Miguel Ángel Gutiérrez de Anda, Arturo Sarmiento-Reyes:
On the interpretation of the time-varying eigenvalues. 301-304 - Albert Kern, Ruedi Stoop, M. Göpfert, D. A. Smirnov, B. B. Bezrucko:
Signal processing in insect hearing organs. 305-308 - Håkan Magnusson, Håkan K. Olsson:
A cross-coupled dual-loop feedback power amplifier driver. 309-312 - David Murphy, Min Qu, John Buckley, Michael Peter Kennedy:
Observations on the relationship between energy transfer efficiency and phase noise in an LC oscillator. 313-316 - David O'Neill, David Bourke, Michael Peter Kennedy:
The Devil's Staircase as a method of comparing injection-locked frequency divider topologies. 317-320 - Andreas Kämpe, Håkan Olsson:
An LC-VCO with one octave tuning range. 321-324 - Olujide A. Adeniran, Andreas Demosthenous:
A 92dB 560MHz 1.5V 0.35 μm CMOS operational transconductance amplifier. 325-328 - Hervé Barthélemy, Matthieu Fillaud:
Simple CMOS 1/jLω to inductive transconductance amplifier. 329-332 - Alfio Dario Grasso
CMOS class AB single-to-differential transconductor. 333-336 - Paolo Bruschi
A tunable CMOS transconductor for ultra-low Gm with wide differential input voltage range. 337-340 - Gianluca Giustolisi, Gaetano Palumbo, Maurizio Gaibotti, Michelangelo Pisasale:
Statistical analysis of CMOS current reference. 341-344 - Jan Lundgren
Simplified gate level noise injection models for behavioral noise coupling simulation. 345-348 - David Nilsson, Robert Forchheimer, Magnus Berggren
The electrochemical transistor and circuit design considerations. 349-352 - Timo Rahkonen
Methods for building polynomial device models for frequency domain nonlinear analysis. 353-356 - Catriona M. Lucey, Colin C. Murphy:
On the structure of 2-channel paraunitary finite field multirate filter banks. 357-360 - Gordana Jovanovic-Dolecek
One method for FIR minimum-phase multiplier-free filter design based on cosine and RRS filters. 361-364 - Premysl Ziska, Miroslav Vlcek, Milos Laipert:
Design of digital all-pass filters with equal-ripple group delay frequency response. 365-368 - Nastooh Avesta:
Fuzzy-wavelet-Kalman signal reconstruction. 369-372 - Mirko Gravati, Maurizio Valle
Modelling mismatch effects in CMOS translinear loops and current mode multipliers. 373-376 - Marco Muselli, Alfonso Quarati
Reconstructing positive Boolean functions with shadow clustering. 377-380 - Jun Guo, Norikazu Takahashi, Tetsuo Nishi:
A learning algorithm for improving the classification speed of support vector machines. 381-384 - Rosario Mita, Gaetano Palumbo, Giorgio Fallica:
A fast active quenching and recharging circuit for single-photon avalanche diodes. 385-388 - Drazen Jurisic, Neven Mijat, George S. Moschytz:
Narrow BP active-RC filters with reduced power and sensitivity. 389-392 - Mauro Gaggero
Multiresolution PWL approximations. 393-396 - Stephen P. Arnold, S. M. Prokes, Mona E. Zaghloul
Localized growth and functionalization of silicon nanowires for MEMS sensor applications. 397-400 - Shahram Minaei
Electronically tunable multi-input single-output voltage-mode filter. 401-404 - Alexey Teplinsky, Raymond Flynn, Orla Feely
Dynamical patterns of bang-bang phase-locked loops. 405-408 - David O'Neill, David Bourke, Zhipeng Ye, Michael Peter Kennedy:
Accurate modeling and experimental validation of an injection-locked frequency divider. 409-412 - Michael Parle, Michael Peter Kennedy:
Comments on the effectiveness of the Szabo and Kolumban solution to false lock in sampling PLL frequency synthesizer. 413-416 - Keith O'Donoghue, James P. Gleeson
Influence of a "coupling factor" on the spectrum of a noisy oscillator. 417-420 - Mika Kämäräinen, Mikko Saukoski, Kari Halonen:
A micropower differential charge-balancing switched-capacitor front-end for capacitive microaccelerometers. 421-424 - Matti Paavola, Mika Laiho
A micropower 2 MHz CMOS frequency reference for capacitive sensor applications. 425-428 - Jürgen Fischer, Ettore Amirante, Thomas Nirschl, Philip Teichmann, Stephan Henzler, Doris Schmitt-Landsiedel:
Impact of process parameter variations on the energy dissipation in adiabatic logic. 429-432 - Didier Van Reeth, Georges G. E. Gielen:
A design automation tool for low-power signal filters for use in sensor interfaces. 433-436 - Ewa Hermanowicz, Håkan Johansson:
On designing minimax adjustable wideband fractional delay FIR filters using two-rate approach. 437-440 - Mohammed N. Abdulazim, Heinz G. Göckler:
Design options of the versatile oversampling two-channel SBC-FDFMUX filter bank. 441-444 - Chethan Visweswar, Sanjit K. Mitra:
New linearly tapered window and its application to FIR filter design. 445-448 - Ozan Aktan, I. Faik Baskaya, Günhan Dündar
A single chip solution for text-to-speech synthesis. 449-452 - Hiroki Sato, Akira Hyogo, Keitaro Sekine:
A low voltage OTA using MOSFET in the triode region and cascode current mirror. 453-456 - Vijayakumar Kalyanaraman, Matthias Müller, Sven Simon, Mario Steinert, Holger Gryska:
Power reduction of ASIPs by distributing the workload on several ASIP-instances. 457-460 - Sreeramulu Raghuram Naidu, Fabiano Fragoso Costa
A novel technique for estimating harmonic and inter-harmonic frequencies in power system signals. 461-464 - Kenny Johansson, Oscar Gustafsson
A detailed complexity model for multiple constant multiplication and an algorithm to minimize the complexity. 465-468
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