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21st FCCM 2013: Seattle, WA, USA
- 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2013, Seattle, WA, USA, April 28-30, 2013. IEEE Computer Society 2013, ISBN 978-1-4673-6005-0
- Eric S. Chung, Doug Burger, Mike Butts, Jan Gray, Chuck Thacker, Kees A. Vissers, John Wawrzynek:
Reconfigurable computing in the era of post-silicon scaling [panel discussion]. - Louis Woods, Gustavo Alonso, Jens Teubner
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Parallel Computation of Skyline Queries. 1-8 - Arup De, Maya B. Gokhale, Rajesh Gupta, Steven Swanson
Minerva: Accelerating Data Analysis in Next-Generation SSDs. 9-16 - Robert J. Halstead, Bharat Sukhwani, Hong Min, Mathew Thoennes, Parijat Dube, Sameh W. Asaad, Balakrishna Iyer:
Accelerating Join Operation for Relational Databases with FPGAs. 17-20 - Yu Bai, Abigail Fuentes-Rivera, Michael Riera, Mohammed Alawad
Boosting Memory Performance of Many-Core FPGA Device through Dynamic Precedence Graph. 21-24 - Christopher Dennl, Daniel Ziener
Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration. 25-28 - Kan Shi, David Boland
Accuracy-Performance Tradeoffs on an FPGA through Overclocking. 29-36 - Alexander Brant, Ameer Abdelhadi, Douglas H. H. Sim, Shao Lin Tang, Michael Xi Yue, Guy G. F. Lemieux:
Safe Overclocking of Tightly Coupled CGRAs and Processor Arrays using Razor. 37-44 - Eddie Hung, Fatemeh Eslami, Steven J. E. Wilton:
Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices. 45-52 - Madhura Purnaprajna, Paolo Ienne:
A Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers. 53-56 - Abdulazim Amouri, Hussam Amrouch
Accurate Thermal-Profile Estimation and Validation for FPGA-Mapped Circuits. 57-60 - Aurelio Morales-Villanueva
On-chip Context Save and Restore of Hardware Tasks on Partially Reconfigurable FPGAs. 61-64 - Roger Moussalli, Walid A. Najjar
A High Throughput No-Stall Golomb-Rice Hardware Decoder. 65-72 - Richard Neil Pittman, Alessandro Forin, Antonio Criminisi, Jamie Shotton, Atabak Mahram:
Image Segmentation Using Hardware Forest Classifiers. 73-80 - Qing Sun, Jiang Jiang, Yongxin Zhu, Yuzhuo Fu:
A Reconfigurable Architecture for 1-D and 2-D Discrete Wavelet Transform. 81-84 - Zhi Ping Ang, Akash Kumar
High Speed Video Processing Using Fine-Grained Processing on FPGA Platform. 85-88 - Qijing Huang
The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs. 89-96 - Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu:
Automating Elimination of Idle Functions by Run-Time Reconfiguration. 97-104 - Ritesh Kumar Soni, Neil Steiner, Matthew French:
Open-Source Bitstream Generation. 105-112 - Eric S. Chung, Michael Papamichael:
ShrinkWrap: Compiler-Enabled Optimization and Customization of Soft Memory Interconnects. 113-116 - Rohit Kumar, Ann Gordon-Ross:
PRML: A Modeling Language for Rapid Design Exploration of Partially Reconfigurable FPGAs. 117-120 - Gonzalo Carvajal, Miguel E. Figueroa
Atacama: An Open FPGA-Based Platform for Mixed-Criticality Communication in Multi-segmented Ethernet Networks. 121-128 - Trevor Bunker, Steven Swanson
Latency-Optimized Networks for Clustering FPGAs. 129-136 - Scott Buscemi, William V. Kritikos, Ron Sass:
A Range and Scaling Study of an FPGA-Based Digital Wireless Channel Emulator. 137-144 - Asif Khan, Nirav Dave:
Enabling Hardware Exploration in Software-Defined Networking: A Flexible, Portable OpenFlow Switch. 145-148 - Yingjie Cao, Yongxin Zhu, Xu Wang, Jiang Jiang, Meikang Qiu:
An FPGA Based PCI-E Root Complex Architecture for Standalone SOPCs. 149-152 - Abid Rafique, Nachiket Kapre, George A. Constantinides:
Application Composition and Communication Optimization in Iterative Solvers Using FPGAs. 153-160 - David B. Thomas:
Parallel Generation of Gaussian Random Numbers Using the Table-Hadamard Transform. 161-168 - Ranko Sredojevic, Andrew Wright, Vladimir Stojanovic:
Hardware-Software Codesign for Embedded Numerical Acceleration. 169-172 - B. Sharat Chandra Varma
FAssem: FPGA Based Acceleration of De Novo Genome Assembly. 173-176 - Frederico Pratas, Diego Oriato, Oliver Pell, Ricardo A. Mata
Accelerating the Computation of Induced Dipoles for Molecular Mechanics with Dataflow Engines. 177-180 - Grigorios Mingas, Farhan Rahman, Christos-Savvas Bouganis
On Optimizing the Arithmetic Precision of MCMC Algorithms. 181-188 - Nachiket Kapre:
Exploiting Input Parameter Uncertainty for Reducing Datapath Precision of SPICE Device Models. 189-197 - Simin Xu, Suhaib A. Fahmy
Efficient Large Integer Squarers on FPGA. 198-201 - Martin Langhammer, Bogdan Pasca
Elementary Function Implementation with Optimized Sub Range Polynomial Evaluation. 202-205 - Marc-André Daigneault, Jean-Pierre David:
High-Level Description and Synthesis of Floating-Point Accumulators on FPGA. 206-209 - James Arram, Kuen Hung Tsoi, Wayne Luk, Peiyong Jiang
Reconfigurable Acceleration of Short Read Mapping. 210-217 - Huabin Ruan, Xiaomeng Huang, Haohuan Fu, Guangwen Yang, Wayne Luk, Sébastien Racanière, Oliver Pell, Wenjing Han:
An FPGA-Based Data Flow Engine for Gaussian Copula Model. 218-225 - Miaoqing Huang, Shiming Li:
A Delay-based PUF Design Using Multiplexers on FPGA. 226 - Jiliang Zhang, Yaping Lin, Yongqiang Lu, Ray C. C. Cheung
Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits. 227 - Cheng Liu
A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency. 228 - Jason Cong, Hugh T. Blair
FPGA Simulation Engine for Customized Construction of Neural Microcircuit. 229 - Lin Gan, Haohuan Fu, Wayne Luk, Chao Yang, Wei Xue, Guangwen Yang:
Global Atmospheric Simulation on a Reconfigurable Platform. 230 - Kizheppatt Vipin
An Approach to a Fully Automated Partial Reconfiguration Design Flow. 231 - Kalin Ovtcharov, Ilian Tili, J. Gregory Steffan:
A Multithreaded VLIW Soft Processor Family. 232 - Nandhini Chandramoorthy, Siddharth Advani, Kevin M. Irick, Vijaykrishnan Narayanan:
A Configurable Architecture for a Visual Saliency System and Its Application in Retail. 233 - Shanyuan Gao, Bin Huang, Ron Sass:
The Impact of Hardware Communication on a Heterogeneous Computing System. 234 - Zain-ul-Abdin, Bertil Svensson:
An Evaluation of High-Performance Embedded Processing on MPPAs. 235 - Thomas Schweizer, Dustin Peterson, Johannes Maximilian Kühn, Tommy Kuhn, Wolfgang Rosenstiel:
A Fast and Accurate FPGA-Based Fault Injection System. 236 - Zheming Jin, Jason D. Bakos:
Memory Access Scheduling on the Convey HC-1. 237 - Marco Ceriani, Gianluca Palermo
Exploring Manycore Multinode Systems for Irregular Applications with FPGA Prototyping. 238 - Shuo Li, Nasim Farahini, Ahmed Hemani:
Global Control and Storage Synthesis for a System Level Synthesis Approach. 239
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