default search action
Simone Secchi
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2010 – 2019
- 2019
- [j8]Diego Noja
, Sergio Rolando
A Note on Sign-Changing Solutions to the NLS on the Double-Bridge Graph. Symmetry 11(2): 161 (2019) - 2017
- [j7]Marco Ceriani
Exploring Efficient Hardware Support for Applications with Irregular Memory Patterns on Multinode Manycore Architectures. IEEE Trans. Parallel Distributed Syst. 28(6): 1635-1648 (2017) - 2015
- [j6]Antonino Tumeo
Special Issue on Architectures and Algorithms for Irregular Applications (AAIA) - Guest editors' introduction. J. Parallel Distributed Comput. 76: 1-2 (2015) - 2013
- [c16]Simone Secchi, Marco Ceriani, Antonino Tumeo
Exploring hardware support for scaling irregular applications on multi-node multi-core architectures. ASAP 2013: 309-313 - [c15]Giuseppe Tuveri, Simone Secchi, Paolo Meloni, Luigi Raffo, Emanuele Cannella:
A runtime adaptive H.264 video-decoding MPSoC platform. DASIP 2013: 149-156 - [c14]Marco Ceriani, Gianluca Palermo
Exploring Manycore Multinode Systems for Irregular Applications with FPGA Prototyping. FCCM 2013: 238 - [c13]Marco Ceriani, Simone Secchi, Antonino Tumeo
Exploring manycore multinode systems for irregular applications with FPGA prototyping. Hot Chips Symposium 2013: 1 - [c12]Marco Ceriani, Simone Secchi, Antonino Tumeo
Prototyping hardware support for irregular applications. RAPIDO 2013: 4:1-4:8 - [e2]Antonino Tumeo, John Feo, Oreste Villa, Simone Secchi:
Proceedings of the 3rd Workshop on Irregular Applications - Architectures and Algorithms, IA3 2013, Denver, Colorado, USA, November 17-22, 2013. ACM 2013, ISBN 978-1-4503-2503-5 [contents] - 2012
- [j5]Antonino Tumeo
Designing Next-Generation Massively Multithreaded Architectures for Irregular Applications. Computer 45(8): 53-61 (2012) - [j4]Oreste Villa, Antonino Tumeo
Fast and Accurate Simulation of the Cray XMT Multithreaded Supercomputer. IEEE Trans. Parallel Distributed Syst. 23(12): 2266-2279 (2012) - [j3]Paolo Meloni
Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper. VLSI Design 2012: 580584:1-580584:16 (2012) - [c11]Simone Secchi, Antonino Tumeo
A Bandwidth-Optimized Multi-core Architecture for Irregular Applications. CCGRID 2012: 580-587 - [c10]Alessandro Morari, Antonino Tumeo
Efficient Sorting on the Tilera Manycore Architecture. SBAC-PAD 2012: 171-178 - 2011
- [c9]Antonino Tumeo
Experiences with String Matching on the Fermi Architecture. ARCS 2011: 26-37 - [c8]Simone Secchi, Antonino Tumeo
Contention Modeling for Multithreaded Distributed Shared Memory Machines: The Cray XMT. CCGRID 2011: 275-284 - [c7]John Feo, Oreste Villa, Antonino Tumeo
Irregular applications: architectures & algorithms. IA3@SC 2011: 1-2 - [c6]John Feo, Oreste Villa, Antonino Tumeo
Towards efficient execution of irregular applications: panel outline. IA3@SC 2011: 43-44 - [e1]John Feo, Oreste Villa, Antonino Tumeo, Simone Secchi:
Proceedings of the first workshop on Irregular applications: architectures and algorithm, IA3 2011, Seattle, WA, USA, November 13, 2011. ACM 2011, ISBN 978-1-4503-1121-2 [contents] - 2010
- [j2]Paolo Meloni
An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures. IEEE Embed. Syst. Lett. 2(1): 5-9 (2010) - [c5]Danilo Pani
Self organization on a swarm computing fabric: a new way to look at fault tolerance. Conf. Computing Frontiers 2010: 327-336 - [c4]Simone Secchi, Paolo Meloni
Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures. ISPASS 2010: 194-202 - [c3]Paolo Meloni
Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper. VLSI-SoC 2010: 43-48
2000 – 2009
- 2008
- [c2]Simone Secchi, Francesca Palumbo
A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching. DSD 2008: 141-148 - [c1]Francesca Palumbo
A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs. SAMOS 2008: 96-105 - 2007
- [p1]Francesca Palumbo
A Surface Tension and Coalescence Model for Dynamic Distributed Resources Allocation in Massively Parallel Processors on-Chip. NICSO 2007: 335-345 - 2004
- [j1]A. Pomponio, Simone Secchi
Interior spikes of a singularly perturbed Neumann problem with potentials. Appl. Math. Lett. 17(9): 1025-1031 (2004)
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-04-25 05:58 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: