default search action
4. FPGA 1996: Monterey, CA, USA
- Jonathan Rose, Carl Ebeling:
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, FPGA 1996, Monterey, CA, USA, February 11-13, 1996. ACM 1996, ISBN 0-89791-773-1 - Alireza Kaviani, Stephen Dean Brown:
Hybrid FPGA Architecture. 3-9 - Rick Amerson, Richard J. Carter, W. Bruce Culbertson, Philip Kuekes, Greg Snider, Lyle Albertson:
Plasma: An FPGA for Million Gate Systems. 10-16 - Kengo Azegami, Shoichiro Kashiwakura, Koichi Yamashita:
Flexible FPGA Architecture Realized of General Purpose SOG. 17-22 - Zeljko Zilic, Zvonko G. Vranesic:
Using BDDs to Design ULMs for FPGAs. 24-30 - Shashidhar Thakur, D. F. Wong
:
Universal Logic Modules for Series-Parallel Functions. 31-37 - Endric Schubert, Wolfgang Rosenstiel:
Combined Spectral Techniques for Boolean Matching. 38-43 - Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses:
The Wave Pipeline Effect on LUT-Based FPGA Architectures. 45-50 - Vi Cuong Chan, David M. Lewis:
Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays. 51-57 - Peichen Pan, C. L. Liu:
Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance. 58-64 - Joel Darnauer, Wayne Wei-Ming Dai:
A Method for Generating Random Circuits and Its Application to Routability Measurement. 66-72 - André DeHon:
Entropy, Counting, and Programmable Interconnect. 73-79 - Yao-Wen Chang, D. F. Wong
Universal Switch-Module Design for Symmetric-Array-Based FPGAs. 80-86 - Adrian Bratt, Ian Macbeth:
Design and Implementation of a Field Programmable Analogue Array. 88-93 - Hans W. Klein:
The EPAC Architecture: An Expert Cell Approach to Field Programmable Analog Devices. 94-98 - Fabrizio Lombardi, David Ashen, Xiao-Tao Chen, Wei-Kang Huang:
Diagnosing Programmable Interconnect Systems for FPGAs. 100-106 - Charles E. Stroud, Ping Chen, Srinivasa Konala, Miron Abramovici:
Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks. 107-113 - André DeHon:
DPGA Utilization and Application. 115-121 - Michael J. Wirthlin, Brad L. Hutchings:
Sequencing Run-Time Reconfigured Hardware with Software. 122-128 - Chris Dick:
Computing the Discrete Fourier Transform on FPGA Based Systolic Arrays. 129-135 - Jason Cong, John Peck, Yuzheng Ding:
RASP: A General Logic Synthesis System for SRAM-Based FPGAs. 137-143 - Darren C. Cronquist, Larry McMurchie:
Emerald: An Architecture-Driven Tool Compiler for FPGAs. 144-150 - Andreas Koch:
Structured Design Implementation: A Strategy for Implementing Regular Datapaths on FPGAs. 151-157
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-29 01:14 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: