default search action
ISCAS 1999: Orlando, Florida, USA - Volume 2
- Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999. IEEE 1999, ISBN 0-7803-5471-0
- Henrik T. Jensen, Joseph F. Jensen:
A low-complexity dynamic element matching technique for reduced-distortion digital-to-analog conversion. 1-4 - Jesper Steensgaard, Un-Ku Moon, Gabor C. Temes:
Mismatch-shaping serial digital-to-analog converter. 5-8 - C. C. Ho, Chung J. Kuo:
Gain mismatch effect of cascaded sigma delta modulator reduced by serial technique. 9-12 - Saska Lindfors, Mika Länsirinne, T. Lindeman, Kari Halonen:
On the design of 2nd order multi-bit Sigma-Delta-modulators. 13-16 - Yngvar Berg, Tor Sverre Lande:
Tunable current mirrors for ultra low voltage. 17-20 - Chi-Hung Lin, Mohammed Ismail:
Design and analysis of an ultra low-voltage CMOS class-AB V-I converter for dynamic range enhancement. 21-24 - J. Francisco Duque-Carrillo, José L. Ausín, Guido Torelli, Juan M. Carrillo
, Pilar Merchán:
Input common-mode feedback technique for very low voltage CMOS amplifiers. 25-28 - Jesper Steensgaard:
Bootstrapped low-voltage analog switches. 29-32 - Ravindranath Naiknaware, Terri S. Fiez:
Time-referenced single-path multi-bit Sigma-Delta ADC using a VCO based quantizer. 33-36 - M. R. Sherkat, Steven B. Bibyk:
A novel decoder for Sigma-Delta modulator providing both high resolution and low latency. 37-40 - Q. Li, Jan Van der Spiegel, Kenneth R. Laker:
A low-voltage/low-power second-order ΣΔ modulator with signal adaptive control architecture. 41-44 - Y. Botteron, Behrouz Nowrouzian, Arthur T. G. Fuller:
Design and switched-capacitor implementation of a new cascade-of-resonators Sigma-Delta converter configuration. 45-48 - E. Bidari, Mustafa Keskin, Franco Maloberti, Un-Ku Moon, Jesper Steensgaard, Gabor C. Temes:
Low-voltage switched-capacitor circuits. 49-52 - S. Karthikeyan, A. Tammineedi, C. Boecker, Edward K. F. Lee:
A 1 V front-end interface for switched-op amp circuits. 53-56 - Seng-Pan U., Rui Paulo Martins, José E. Franca:
Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity. 57-60 - Mikko Waltari, Kari Halonen:
Timing skew insensitive switching for double sampled circuits. 61-64 - Luis G. Bustamante, Michael A. Soderstrand:
High-range switched-capacitor tracking filter. 65-68 - Raffaele Boi, Simona Brigati, Fabrizio Francesconi, Carla Ghidini, Piero Malcovati, Franco Maloberti, Matteo Poletti:
Switched-capacitor Litton-code matched filter for satellite ODBH bus. 69-72 - Antonio Petraglia, Jacqueline S. Pereira:
Switched-capacitor decimation filters with direct form polyphase structure having very small sensitivity characteristics. 73-76 - Seng-Pan U., Rui Paulo Martins, José E. Franca:
High performance multirate SC circuits with predictive correlated double sampling technique. 77-80 - Ramachandra Achar, Michel S. Nakhla:
Efficient simulation of on-chip RF components using model-reduction techniques. 81-84 - Shijun Yang, Ralph Mason, Calvin Plett:
6.5 mW CMOS low noise amplifier at 1.9 GHz. 85-88 - Abdelohahab Djemouai, Mohamad Sawan, Mustapha Slamani:
A 200 MHz frequency-locked loop based on new frequency-to-voltage converters approach. 89-92 - Hormoz Djahanshahi, C. André T. Salama:
Differential 0.35µm CMOS circuits for 622 MHz/933 MHz monolithic clock and data recovery applications. 93-96 - G. P. Hartman, Kenneth W. Martin, Angus McLaren:
Continuous-time adaptive-analog coaxial cable equalizer in 0.5 um CMOS. 97-100 - Shenhong Wang, M. Omair Ahmad:
A switched-current ratio-independent algorithmic D/A converter. 101-104 - Chunyan Wang, M. Omair Ahmad, M. N. S. Swamy:
Design of a transistor-mismatch-insensitive switched-current memory cell. 105-108 - Sassan Tabatabaei, André Ivanov:
A built-in current monitor for testing analog circuit blocks. 109-114 - Amr M. Fahim, Mohamed I. Elmasry:
A low-power CMOS frequency synthesizer design methodology for wireless applications. 115-119 - Soliman A. Mahmoud, Ahmed M. Soliman:
The current-feedback differential difference amplifier: new CMOS realization with rail to rail class-AB output stage. 120-123 - Domine M. W. Leenaerts:
A new concept for flash AD conversion. 124-127 - Hanspeter Schmid, George S. Moschytz:
A tunable, video-frequency, low-power, single-amplifier biquadratic filter in CMOS. 128-131 - Yusuhiro Sugimoto, Shigeo Imai:
The design of a 1 V, 40 MHz, current-mode sample-and-hold circuit with 10-bit linearity. 132-135 - Chi-Hung Lin, Mohammed Ismail:
A 2 V 5th-order fully-differential CMOS Gm-C filter for wideband communication. 136-139 - Costantino Pala, Gerd Schuppener, Mehran Mokhtari:
A 6 GHz, 1.8 V, divide-by-2 circuit implemented in silicon bipolar technology. 140-143 - Mohamed Dessouky, Andreas Kaiser:
Rail-to-rail operation of very low voltage CMOS switched-capacitor circuits. 144-147 - F. Dudek, Bashir M. Al-Hashimi, M. Moniri:
Compensation of nonideal effects in video-frequency sinc(x)-equalizers using tunable gm-C structure. 148-151 - Lizhong Sun, Thierry Lepley, Franck Nozahic, Amaud Bellissant, Tad A. Kwasniewski, Bany Heim:
Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis. 152-155 - Phanumas Khumsat, Alison J. Payne:
Low-noise, low-distortion Gilbert current gain-cell and Gilbert cell transconductor. 156-159 - Rami Ahola, Kari Stadius, Kari Halonen:
Design of a fully integrated 2 GHz CMOS frequency synthesizer. 160-163 - Meng Tong Tan, Joseph Sylvester Chang, Yit Chow Tong:
A novel self-tuning pulse width modulator based on master-slave architecture for a Class D amplifier. 164-167 - P. Costa, Carlo Fiocchi, Umberto Gatti, Franco Maloberti:
High-performance BiCMOS output buffer design strategies. 168-171 - Alexandre Schmid, D. Bowler, R. Baumgartner, Yusuf Leblebici:
A novel analog-digital flash converter architecture based on capacitive threshold gates. 172-175 - Lizhong Sun, Tad A. Kwasniewski, Kris Iniewski:
A quadrature output voltage controlled ring oscillator based on three-stage sub-feedback loops. 176-179 - Leonard A. MacEachern, Eyad Abou-Allam, L. Wang, Tajinder Manku:
Low voltage mixer biasing using monolithic integrated transformer dc-coupling. 180-183 - Dominique Python, Christian C. Enz:
An antialiasing filter using complementary MOS transconductors biased in the triode region. 184-187 - Eric W. Justh, Francis J. Kub:
Analog CMOS high-frequency continuous wavelet transform circuit. 188-191 - Omid Oliaei:
Clock jitter noise spectra in continuous-time delta-sigma modulators. 192-195 - Giuseppe Palmisano, Salvatore Pennisi:
A 20-dB CMOS IF amplifier with embedded single-to-differential input converter. 196-199 - Alberto Yufera, Adoración Rueda:
Programmable low-voltage continuous-time filter for audio applications. 200-203 - Arie van Staveren, T. H. A. J. Cordenier, F. C. M. Kuijstermans, Pieter van der Kloet, Fred L. Neerhoff, Chris J. M. Verhoeven, Arthur H. M. van Roermund:
The linear time-varying approach applied to the design of a negative-feedback class-B output amplifier. 204-207 - Martin Lantz, Henrik Floberg:
Bipolar, wideband, bias current source. 208-211 - Carlo Fiocchi, Umberto Gatti:
A very flexible BiCMOS low-voltage high-performance source follower. 212-215 - Ramkishore Ganti, L. Richard Carley, Brent A. Myers:
A low distortion high frequency transconductor structure. 216-219 - S. Kumar, A. Govil, A. Bhattacharyya, D. Dutta:
A wide-range tunable bandpass filter cum sinusoidal oscillator using a new current-controlled resistor. 220-223 - Spiridon Vlassis, Stilianos Siskos:
High speed and high resolution WTA circuit. 224-227 - Todd Hinck, Z. Yang, Q. Zhang, Allyn E. Hubbard:
A current-mode implementation of a traveling wave amplifier model similar to the cochlea. 228-231 - R. Kalim, Denise M. Wilson:
Semi-parallel rank-order filtering in analog VLSI. 232-235 - Bradley A. Minch, Paul E. Hasler, Chris Diorio:
Synthesis of multiple-input translinear element networks. 236-239 - Alberto Pesavento, Christof Koch:
A wide linear range four quadrant multiplier in subthreshold CMOS. 240-243 - Manuel Domínguez Pumar, Luis M. Castañer:
Bounding of thermal Sigma-Delta modulators output for sensors. 244-247 - Pak Kwong Chan, L. S. Ng, Liter Siek
Bulk compensated CMOS squaring circuits. 248-251 - Bo Shi, Lars Sundström
Design and implementation of a CMOS power feedback linearization IC for RF power amplifiers. 252-255 - Wei-Shinn Wey, Yu-Chung Huang:
A CMOS RMS-to-DC converter using ΣΔ multiplier-divider. 256-258 - Abdelohahab Djemouai, Mohamad Sawan, Mustapha Slamani:
An efficient RF power transfer and bidirectional data transmission to implantable electronic devices. 259-262 - Khaled Hayatleh, W. J. Su, F. J. Lidgey:
Improved current-feedback op-amp with good DC and CMRR performance. 263-266 - Ali Toker, Serdar Özoguz, Oguzhan Cicekoglu:
High output impedance current-mode multifunction filter using FTFNs. 267-269 - Erik Bruun
On dynamic range limitations of CMOS current conveyors. 270-273 - Akira Hyogo, Y. Fukutomi, Keitaro Sekine:
Low voltage four-quadrant analog multiplier using square-root circuit based on CMOS pair. 274-277 - Ravindranath Naiknaware, Terri S. Fiez:
Switched-capacitor integrator design optimizing for power and process variations. 278-281 - Petr Simek, Vladislav Musil:
An advanced S3I sigma-delta modulator with reduced distortion. 282-285 - Julius Georgiou, Emmanuel M. Drakakis, Christofer Toumazou, P. Premanoj:
An analogue micropower log-domain silicon circuit for the Hodgkin and Huxley nerve axon. 286-289 - Eric Fogleman, Ian Galton, Henrik Jensen:
A dynamic element matching technique for reduced-distortion multibit quantization in delta-sigma ADCs. 290-293 - Joseph S. Shor, Vladimir Koifman, Yachin Afek:
Novel method to compensate for resistor non-linearities and its application to the integration of analog functions on system-on-a-chip ICs. 294-297 - Peter B. Aronhime, Zbigniew Lata, Jie Deng, Brent Maundy:
Effects of parasitic admittances in active synthesis of current-mode circuits. 298-301 - Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Andreas G. Andreou:
A general subthreshold MOS translinear theorem. 302-305 - Zihua Guo, Oscar C. Au:
Map automatic input based on NN and GAs. 306-309 - Hsin-Shu Chen, A. Ito:
Characterization of 1/f noise vs. number of gate stripes in MOS transistors. 310-313 - Radu M. Secareanu, Eby G. Friedman:
A high precision CMOS current mirror/divider. 314-317 - R. Brannen, Hassan O. Elwan, Mohammed Ismail:
A simple low-voltage all MOS linear-dB AGC/multiplier circuit. 318-321 - François Kaess, Riad Kanan
Performance/power tradeoffs in high-speed GaAs ADCs. 322-325 - Zhiliang Zheng, Un-Ku Moon, Jesper Steensgaard, Bo Wang, Gabor C. Temes:
Capacitor mismatch error cancellation technique for a successive approximation A/D converter. 326-329 - Huawen Jin, Edward K. F. Lee:
A digital technique for reducing clock jitter effects in time-interleaved A/D converter. 330-333 - Alberto L. Sangiovanni-Vincentelli, Marco Re, Luciano Lavagno, Gian Carlo Cardarilli, Roberto Lojacono:
Analysis of the quantization noise effects on the SQNR behaviour in analog to digital conversion. 334-338 - Daniele Gardino, Franco Maloberti:
High resolution rail-to-rail ADC in CMOS digital technology. 339-342 - B. E. Jonsson, Hannu Tenhunen:
A dual 3-V 32-MS/s CMOS switched-current ADC for telecommunication applications. 343-346 - Eric Fogleman, Ian Galton, Henrik Jensen:
An area-efficient differential input ADC with digital common mode rejection. 347-350 - B. E. Jonsson, Hannu Tenhunen:
A 3 V switched-current pipelined analog-to-digital converter in a 5 V CMOS process. 351-354 - Jürgen A. E. P. van Engelen, Rudy J. van de Plassche:
Stability and design of continuous-time bandpass sigma delta modulators. 355-359 - Hassan Aboushady, Elizabeth de Lira Mendes, Mohamed Dessouky, Patrick Loumeau:
A current-mode continuous-time Sigma-Delta modulator with delayed return-to-zero feedback. 360-363 - Luis Hernández, Susana Patón:
A continuous-time noise-shaping modulator for logarithmic A/D conversion. 364-367 - Chi-Hung Lin, Chunlei Shi, Mohammed Ismail, Gyu Moon:
A 5 MHz Nyquist rate continuous-time sigma-delta modulator for wideband wireless communication. 368-371 - Tsung-Yuan Chang, Steven B. Bibyk:
Exact analysis of second order bandpass delta-sigma modulator with sinusoidal inputs. 372-375 - Godi Fischer, Deokhwan Hyun:
Limit cycles in single-stage delta-sigma modulators. 376-379 - Saman S. Abeysekera, Xue Yao, Zhuquan Zang:
A comparison of various low-pass filter architectures for sigma-delta demodulators. 380-383 - Simona Brigati, Fabrizio Francesconi, Piero Malcovati, Davide Tonietto, Andrea Baschirotto, Franco Maloberti:
Modeling sigma-delta modulator non-idealities in SIMULINK(R). 384-387 - Paul E. Hasler, Bradley A. Minch, Chris Diorio:
Floating-gate devices: they are not just for digital memories any more. 388-391 - Atsuhiko Okada, Tadashi Shibata:
A neuron-MOS parallel associator for high-speed CDMA matched filter. 392-395 - Yngvar Berg, Tor Sverre Lande:
Area efficient circuit tuning with floating-gate techniques. 396-399 - Bradley A. Minch, Paul E. Hasler:
A floating-gate technology for digital CMOS processes. 400-403 - Reid R. Harrison:
Floating gate current mirror for gain correction in CMOS translinear circuits. 404-407 - Jaime Ramírez-Angulo, Ramón González Carvajal, Jonathan Noel Tombs, Antonio Jesús Torralba Silgado:
Low voltage CMOS op-amps for a supply close to a transistor's threshold voltage. 408-411 - Paul E. Hasler, Paul D. Smith:
An autozeroing floating-gate amplifier with gain adaptation. 412-415 - Philipp Häfliger, Christoph Rasche:
Floating gate analog memory for parameter and variable storage in a learning silicon neuron. 416-419 - Riad Kanan
A 640 mW high accuracy 8-bit 1 GHz flash ADC encoder. 420-423 - Felix Lustenberger, Markus Helfenstein, Hans-Andrea Loeliger, Felix Tarköy, George S. Moschytz:
An analog VLSI decoding technique for digital codes. 424-427 - Markus Helfenstein, Felix Lustenberger, Andrea Loeliger, Felix Tarköy, George S. Moschytz:
High-speed interfaces for analog, iterative VLSI decoders. 428-431 - Kai He, Gert Cauwenberghs:
An area-efficient analog VLSI architecture for state-parallel Viterbi decoding. 432-435 - Tuna B. Tarim, Mohammed Ismail:
Functional yield enhancement and statistical design of a low power transconductor. 436-439 - R. A. Rafla, Mourad N. El-Gamal:
Design of a 1.5 V CMOS integrated 3 GHz LNA. 440-443 - Sudip Chakrabarti, Abhijit Chatterjee:
Fault modeling and fault sampling for isolating faults in analog and mixed-signal circuits. 444-447 - Junwei Hou, William H. Kao, Abhijit Chatterjee:
A novel concurrent fault simulation method for mixed-signal circuits. 448-451 - Bruce J. Tesch, Philip M. Pratt, Kanti Bacrania, Mario Sanchez:
A 14-b, 125 MSPS digital-to-analog converter and bandgap voltage reference in 0.5 um CMOS. 452-455 - Apisak Worapishet, John B. Hughes, Christofer Toumazou:
Class AB technique for high performance switched-current memory cells. 456-459 - John B. Hughes, Kenneth W. Moulding:
Error neutralisation in switched current memory cells. 460-463 - Apisak Worapishet, John B. Hughes, Christofer Toumazou:
Error neutralised switched-current comparator. 464-467 - Andrew E. J. Ng, John I. Sewell:
Pseudo-N-path cells for switched-current signal processing. 468-471 - Fathi A. Farag, Carlos Galup-Montoro, Márcio C. Schneider:
A programmable low voltage switched-current FIR filter. 472-475 - José M. de la Rosa, Maria Belen Pérez-Verdú, Rocío del Río, Ángel Rodríguez-Vázquez:
Non-ideal quantization noise shaping in switched-current bandpass Sigma-Delta modulators. 476-479 - Antônio Carlos M. de Queiroz, Jones Schechtman:
Sensitivity and error reduction by component swapping in switched-current filters. 480-483 - Andrew E. J. Ng, John I. Sewell:
Bilinear transformed switched-current ladder interpolators. 484-487 - Shunji Kimura
Circuit design technologies for high-speed lightwave communications beyond 40 Gbit/s. 488-491 - Berthold Wedding, Werner Pöhlmann, D. Schlump, E. Schlag, R. Ballentin:
SiGe circuits for high bit-rate optical transmission systems. 492-495 - Thorsten Baumheinrich, Ulrich Langmann:
Design of high speed bipolar Si/SiGe ICs for optical wide band communications. 496-499 - Mark J. W. Rodwell, Q. Lee, Dino Mensa, J. Guthrie, Yoram Betser, Suzanne C. Martin, R. P. Smith, S. Jaganathan, Thomas Mathew, P. Krishnan, C. Serhan, Stephen I. Long:
Ultra high frequency integrated circuits using transferred substrate heterojunction bipolar transistors. 500-503 - Philippe André, Nicolas Kauffmann, Patrick Desrousseaux, Jean Godin, Agnieszka Konczykowska:
InP HBT circuits for high speed ETDM systems. 504-507 - Mehrun Mokhtari, Ali Ladjemi, Urban Westergren, Lars Thylén:
Bit-rate transparent electronic data regeneration in repeaters for high speed lightwave communication systems. 508-511 - Thomas Meincke, Ahmed Hemani, Shashi Kumar, Peeter Ellervee, Johnny Öberg, Thomas Olsson, Peter Nilsson, Dan Lindqvist, Hannu Tenhunen:
Globally asynchronous locally synchronous architecture for large high-performance ASICs. 512-515 - Fenghao Mu, Christer Svensson:
High speed interface for system-on-chip design by self-tested self-synchronization. 516-519 - Woogeun Rhee:
Design of low-jitter 1-GHz phase-locked loops for digital clock generation. 520-523 - Thomas Toifl, Paulo Moreira:
A radiation-hard 80 MHz phase locked loop for clock and data recovery. 524-527 - Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen:
A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop. 528-531 - Yasuaki Sumi, Shigeki Obote, Naoki Kitai, Ryousuke Furuhashi, Yoshitaka Matsuda, Yutaka Fukui:
PLL frequency synthesizer with an auxiliary programmable divider. 532-536 - Antti Mäntyniemi, Timo Rahkonen, Juha Kostamovaara:
A high resolution digital CMOS time-to-digital converter based on nested delay locked loops. 537-540 - Fenghao Mu, Christer Svensson:
High speed multistage CMOS clock buffers with pulse width control loop. 541-544 - W. Rhee:
Design of high-performance CMOS charge pumps in phase-locked loops. 545-548 - Amr N. Hafez, Mohamed I. Elmasry:
A low power monolithic subsampled phase-locked loop architecture for wireless transceivers. 549-552 - Hyuk-Jun Sung, Kwang Sub Yoon:
A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range. 553-556 - Pietro Andreani, Sven Mattisson:
A 2.4-GHz CMOS monolithic VCO based on an MOS varactor. 557-560 - Yi-Chang, Edwin W. Greeneich:
A current-controlled oscillator coarse-steering acquisition-aid for high frequency SOI CMOS PLL circuits. 561-564 - L. Wu, Huiting Chen, S. Nagavarapu, Randall L. Geiger, Edward Lee, W. Black:
A monolithic 1.25 Gbits/sec CMOS clock/data recovery circuit for fibre channel transceiver. 565-568 - Huiting Chen, Edward Lee, Randall L. Geiger:
A 2 GHz VCO with process and temperature compensation. 569-572 - Yorgos Koutsoyannopoulos, Yannis Papananos, Sotiris Bantas, Carlo Alemanni:
Novel Si integrated inductor and transformer structures for RF IC design. 573-576 - Mehmet Ozgur, Mona E. Zaghloul, Michael Gaitan:
High Q backside micromachined CMOS inductors. 577-580 - Sotiris Bantas, Yannis Papananos, Yorgos Koutsoyannopoulos:
CMOS tunable bandpass RF filters utilizing coupled on-chip inductors. 581-584 - Chi-Wa Lo, Howard C. Luong:
2-V 900-MHz quadrature coupled LC oscillators with improved amplitude and phase matchings. 585-588 - D. L. C. Leung, Howard C. Luong:
A fourth-order CMOS bandpass amplifier with high linearity and high image rejection for GSM receivers. 589-592 - Sherif H. Galal, Maged S. Tawfik, Hani F. Ragaie:
On the design and sensitivity of RC sequence asymmetric polyphase networks in RF integrated transceivers. 593-597 - Ganesh Kathiresan, Christofer Toumazou:
A low voltage bulk driven downconversion mixer core. 598-601 - Steve Hung-Lung Tu, Christofer Toumazou:
Design of highly-efficient power-controllable CMOS class E RF power amplifiers. 602-605 - G. Xu, Sherif H. K. Embabi, P. Hao, Edgar Sánchez-Sinencio:
A low voltage fully differential nested Gm capacitance compensation amplifier: analysis and design. 606-609 - Mark Schlarmann, Edward K. F. Lee, Randall L. Geiger:
A new multipath amplifier design technique for enhancing gain without sacrificing bandwidth. 610-615 - Ka Nang Leung
Optimum nested Miller compensation for low-voltage low-power CMOS amplifier design. 616-619 - Jaime Ramírez-Angulo:
Linear amplifiers architectures with very high gain-bandwidth product. 620-623 - Bahram Zand, Khoman Phang, David A. Johns:
Transimpedance amplifier with differential photodiode current sensing. 624-627 - Mohamed Mostafa, Hassan O. Elwan, Abdellatif Bellaour, Brad Kramer, Sherif H. K. Embabi:
A 110 MHz 70 dB CMOS variable gain amplifier. 628-631 - Hassan O. Elwan, Weinan Gao, Roberto Sadkowski, Mohammed Ismail:
A low voltage CMOS class AB operational transconductance amplifier. 632-635 - Adrian Ryan, Marius Neag, Oliver McCarthy:
CMOS operational transconductance amplifier for PRML read channel applications. 636-639 - Jader A. De Lima, Carlos Dualibe:
A tunable triode-MOSFET transconductor and its application to gm-C filters. 640-643 - Y. Ro, William R. Eisenstadt, Robert M. Fox:
New 1.4 volt transconductor with superior power supply rejection. 644-647 - José Silva-Martínez, S. Solis-Bustos:
Design considerations for high performance very low frequency filters. 648-651 - D. H. Chiang, R. Schaumann:
Comparison of magnitude and delay sensitivity in IFLF and cascade g m-C filters. 652-655 - Yuyu Chang, John Choma Jr., Jack Wills:
A CMOS continuous-time active biquad filter for gigahertz-band applications. 656-659 - P. H. Shanjani, Seyed Mojtaba Atarodi
A high dynamic-range, self-tuned Gm-C filter for video-range applications. 660-663 - Narendra Rao, Vishnu Balan, Richard Contreras, Jenn-Gang Chern, Y. Wang:
A 150 MHz continuous-time seventh order 0.05° equiripple linear phase filter. 664-666 - Aydin I. Karsilayan
Automatic tuning of high-Q filters based on envelope detection. 668-671 - Douglas Frey:
On instantaneous vs. syllabic companding in log domain filters. 672-676 - Sergio Callegari
Improved bandwidth, low voltage log domain building blocks. 677-680 - Mourad N. El-Gamal, Gordon W. Roberts:
A 1.2 V NPN-only log-domain integrator. 681-684 - Dominique Python, Manfred Punzenberger, Christian C. Enz:
A 1-V CMOS log-domain integrator. 685-688 - R. M. Fox, M. Nagarajan:
Multiple operating points in a CMOS log-domain filter. 689-692 - Emmanuel M. Drakakis, Alison J. Payne:
Structured log-domain synthesis of nonlinear systems. 693-696 - Bradley A. Minch:
Synthesis of multiple-input translinear element log-domain filters. 697-700 - Wouter A. Serdijn, Jan Mulder, Michiel H. L. Kouwenhoven, Arthur H. M. van Roermund:
A low-voltage translinear second-order quadrature oscillator. 701-704
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-29 01:15 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: