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PARELEC 2004: Dresden, Germany
- 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 7-10 September 2004, Dresden, Germany. IEEE Computer Society 2004, ISBN 0-7695-2080-4
Invited Talks
- Hartmut Schmeck:
Organic Computing-Vision and Challenge for System Design. 3 - Andreas Blaszczyk:
The Role of Parallel Computing at ABB Corporate Research Switzerland. 4-
Session A1: Parallel System Architectures I
- Carsten Clauss, Martin Pöppe, Thomas Bemmerl:
Optimising MPI Applications for Heterogeneous Coupled Clusters with MetaMPICH. 7-12 - Georgios Tsilikas, Martin Fleury:
Matrix Multiplication Performance on Commodity Shared-Memory Multiprocessors. 13-18 - Adam Smyk, Marek S. Tudruj:
Parallel Implementation of FDTD Computations Based on Macro Data Flow Paradigm. 19-24 - Henryk Krawczyk, Tomasz Madajczak:
Optimal Programming of Critical Sections in Modern Network Processors under Performance Requirements. 25-30
Session B1: Design and Design Automation I
- Dirk Fimmel, Stefan Quitzk, Wolfgang Schwarz:
Large-Scale Tolerance Analysis. 33-38 - Jie Guo, Michael Hosemann, Gerhard P. Fettweis:
Employing Compilers for Determining Architectural Features of Application-Specific DSPs. 39-44 - Gordon Cichon, Pablo Robelly, Hendrik Seidel, Marcus Bronzel, Gerhard P. Fettweis:
Compiler Scheduling for STA-Processors. 45-50 - Daniel Matolin, Jörg Schreiter, Stefan Getzlaff, René Schüffny:
An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation. 51-55
Session A2: Methods for Parallelization
- Lukasz Masko, Grégory Mounié, Denis Trystram, Marek S. Tudruj:
Moldable Task Scheduling in Dynamic SMP Clusters with Communication on the Fly. 59-64 - Lukasz Masko:
Program Graph Scheduling for SMP Clusters with Communication on-the-Fly Based on Extended DS Approach. 65-70 - Tomasz Madajczak:
An Optimal Abstraction Model for Hardware Multithreading in Modern Processor Architectures. 71-76
Session B2: Methods for Automatic Parallelization
- Frank Hannig, Jürgen Teich:
Dynamic Piecewise Linear/Regular Algorithms. 79-84 - Sebastian Siegel, Renate Merker:
Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays. 85-90 - Wlodzimierz Bielecki, Rafal Kocisz:
A Modified Vertex Method for Parallelization of Arbitrary Nested Loops. 91-96
Session A3: Specification and Modeling of Parallel Systems
- Stanislaw Chrobot:
Introducing Variable Sharing to Process Calculi. 99-104 - Christian Dufour, Jean Bélanger:
A PC-Based Real-Time Parallel Simulator of Electric Systems and Drives. 105-113 - Uwe Hatnik, Sven Altmann:
Using ModelSim, Matlab/Simulink and NS for Simulation of Distributed Systems. 114-119
Session B3: Parallel System Architectures II
- Noboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano:
A New Memory Module for Memory Intensive Applications. 123-128 - Christian Sauer, Matthias Gries, José Ignacio Gómez, Scott J. Weber, Kurt Keutzer:
Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express. 129-134 - Rolf Hoffmann, Wolfgang Heenes, Mathias Halbach:
Implementation of the Massively Parallel Model GCA. 135-139
Session A4: Numerical Methods for Parallel Processing I
- Andrzej Jordan, Pawel B. Myszkowski, Konrad Radzik:
The Parallel Computations for the Linear State Equations. 143-145 - Peter Benner, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí:
Computing Passive Reduced-Order Models for Circuit Simulation. 146-151 - Wojciech Walendziuk, Andrzej Jordan, Adam Skorek:
Visualization of the Parallel Finite-Difference Time-Domain Method Computations Results. 152-155 - Wojciech Bozejko, Mieczyslaw Wodecki:
Parallel Tabu Search Method Approach for Very Difficult Permutation Scheduling Problems. 156-161
Session B4: Reconfigurable Computing I
- Lev Kirischian, Irina Terterian, Pil Woo Chun, Vadim Geurkov:
Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-Architecture. 165-170 - Tobias Oppold, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel:
A Design Environment for Processor-Like Reconfigurable Hardware. 171-176 - Jörg Schneider, Vincent Kotzsch, Steffen Rülke:
Demonstrator: Reuse Automation for Reconfigurable System-on-Chip Design within a DVB Environment. 177-180 - Andreas Kühn, Sorin A. Huss:
Dynamically Reconfigurable Hardware for Object-Oriented Processing. 181-186
Session A5: Numerical Methods for Parallel Processing II
- Jaroslaw Forenc, Andrzej Jordan:
The Modified Speculative Method for the Transient States Analysis. 189-193 - Boguslaw Butrylo, Christian Vollaire, Laurent Nicolas:
Limits of the Distributed Finite Element Time Domain Algorithm in Multi-Computer Environment. 194-199 - Przemyslaw Stpiczynski:
Numerical Evaluation of Linear Recurrences on High Performance Computers and Clusters of Workstations. 200-205
Session B5: Embedded Multiprocessors (and Network Processors)
- Matthias Grünewald, Dinh Khoi Le, Uwe Kastens, Jörg-Christian Niemann, Mario Porrmann
, Ulrich Rückert, Adrian Slowik, Michael Thies:
Network Application Driven Instruction Set Extensions for Embedded Processing Clusters. 209-214 - Mathias Kortke, Jan Müller, Rainer Schaffer, Sebastian Siegel, Renate Merker, Jürgen Kelber:
A Parallel Hardware-Software System for Signal Processing Algorithms. 215-220 - Hendrik Seidel, Gordon Cichon, Pablo Robelly, Marcus Bronzel, Gerhard P. Fettweis:
Hardware / Software Co-Design of a SIMD-DSP-Based DVB-T Receiver. 221-225
Session A6: Fault-Tolerant and Evolutionary Systems
- Carsten Maple, Liang Guo, Jie Zhang
Parallel Genetic Algorithms for Third Generation Mobile Network Planning. 229-236 - Bernhard Fechner, Jörg Keller:
A Fault-Tolerant Voting Scheme for Multithreaded Environments. 237-239 - Anna Derezinska
Estimating Dependability of Parallel FFT Application using Fault Injection. 240-245 - Jamil Saif, Henryk Krawczyk:
Tuning of Parallel ROI Matching Algorithms. 246-248
Session B6: Reconfigurable Computing II
- Dietmar Fey, Lutz Hoppe, Andreas Loos:
Reconfigurable On-Chip SIMD Processor Architectures for Intelligent CMOS Camera Chips. 251-255 - Eryk Laskowski:
Program Scheduling in Look-Ahead Reconfigurable Parallel Systems with Multiple Communication Resources. 256-261 - V. G. Khoroshevsky:
Architecture and Functioning of Large-Scale Distributed Reconfigurable Computer Systems. 262-267
Session A7: Parallel Software Environments I
- Claudia Roberta Calidonna, Mario Mango Furnari:
The Cellular Automata Network Compiler System: Modules and Features. 271-276 - Torsten Mehlan, Wolfgang Rehm, Ralph Engler, Tobias Wenzel:
Providing a High-Performance VIA-Module for LAM/MPI. 277-282 - Peter Buchholz, Andriy Panchenko:
An EM Algorithm for Fitting of Real Traffic Traces to PH-Distribution. 283-288 - Silvio Misera, Heinrich Theodor Vierhaus:
FIT - A Parallel Hierarchical Fault Simulation Environment. 289-294
Session B7: Real Time Parallel Computing I
- A. S. Nepomniaschaya, Zbigniew Kokosinski:
Associative Graph Processor and Its Properties. 297-302 - Grzegorz Pastuszak:
A Novel Architecture of Arithmetic Coder in JPEG2000 Based on Parallel Symbol Encoding. 303-308 - Marc Franzmeier, Christopher Pohl, Mario Porrmann
Hardware Accelerated Data Analysis. 309-314 - Axel Siebenborn, Oliver Bringmann, Wolfgang Rosenstiel:
Communication Analysis for Network-on-Chip Design. 315-320
Session A8: Parallel Software Environments II
- Damian Kopanski, Janusz Borkowski, Marek S. Tudruj:
Co-Ordination of Parallel GRID Applications using Synchronizers. 323-327 - Janusz Borkowski:
Parallel Program Control Based on Hierarchically Detected Consistent Global States. 328-333 - Robert Piotr Bycul:
A Graphical Interface to a Parallel Solver: PSGE Description Through an Application. 334-337
Session B8: Real Time Parallel Computing II
- Sylvain Alliot, Laurentiu Nicolae, Martijn van Veelen:
A Tool for Exploring the Large Scale Signal Processing Systems Specification. 341-348 - Jork Löser, Hermann Härtig:
Using Switched Ethernet for Hard Real-Time Communication. 349-353 - A. Rodríguez, A. González, Manuel P. Malumbres
Performance Evaluation of Parallel MPEG-4 Video Coding Algorithms on Clusters of Workstations. 354-357
Posters
- Georgios Dimitriou, Constantine D. Polychronopoulos:
Loop Scheduling for Multithreaded Processors. 361-366 - Pawel Kaczmarek, Henryk Krawczyk:
Influence of Exception Handling on Distributed Applications. 367-371 - Pablo Robelly, Gordon Cichon, Hendrik Seidel, Gerhard P. Fettweis:
Automatic Code Generation for SIMD DSP Architectures: An Algebraic Approach. 372-375 - Erik Vonnahme, Björn Griese, Mario Porrmann
Dynamic Reconfiguration of Real-Time Network Interfaces. 376-379 - Victor E. Malyshkin, I. Naumkin, N. Malyshkin, Vladimir D. Korneev, Michael Ostapkevich:
Digital Electromagnetic Model of the Power System: Parallel Implementation for Multicomputers. 380-385 - Marek S. Tudruj, Lukasz Masko:
Fine-Grain Numerical Computations in Dynamic SMP Clusters with Communication on the Fly. 386-389 - Pawel Czarnul, Arkadiusz Urbaniak, Marcin Fraczak, Maciej Dyczkowski, Bartlomiej Balcerek:
Towards Easy-to-Use Checkpointing of MPI Applications within CLUSTERIX. 390-393 - Octav Brudaru, Octavian Buzatu:
Distributed Genetic Algorithm for Finding Fuzzy Rational Approximators. 394-397 - Eryk Laskowski, Richard Olejnik, Bernard Toursel, Marek S. Tudruj:
Scheduling Byte Code-Defined Data Dependence Graphs of Object Oriented Programs. 398-401
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