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IEEE Transactions on Very Large Scale Integration Systems, Volume 30
Volume 30, Number 1, January 2022
- Massimo Alioto
:
Editorial Opening of the 2022 TVLSI Editorial Year - Connecting Trends From Society to VLSI Systems. 1-4 - Makoto Nagata
Physical Attack Protection Techniques for IC Chip Level Hardware Security. 5-14 - Tuotian Liao
High-Dimensional Many-Objective Bayesian Optimization for LDE-Aware Analog IC Sizing. 15-28 - Yue-Ming Wu
A 68-GHz Loss Compensated Distributed Amplifier Using Frequency Interleaved Technique in 65-nm CMOS Technology. 29-39 - Ragh Kuttappa
Multiphase Digital Low-Dropout Regulators. 40-50 - Ghassem Jaberipur
Impact of Radix-10 Redundant Digit Set [-6, 9] on Basic Decimal Arithmetic Operations. 51-59 - Nicholas A. Lanzillo
Power Delivery Design, Signal Routing, and Performance of On-Chip Cobalt Interconnects in Advanced Technology Nodes. 60-67 - Priyesh Shukla
Ultralow-Power Localization of Insect-Scale Drones: Interplay of Probabilistic Filtering and Compute-in-Memory. 68-80 - Ning-Chi Huang
Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs. 81-94 - Weidong Zhang
EddySuperblock: Improving NAND Flash Efficiency and Lifetime by Endurance-Driven Dynamic Superblock Management. 95-107 - Sumit Walia
Fast and Low-Power Quantized Fixed Posit High-Accuracy DNN Implementation. 108-111 - Moslem Heidarpur
Corrections to "An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FPGA Implementation". 112
Volume 30, Number 2, February 2022
- Lianxi Liu
A 0.8-V, 2.55-GHz, 2.62-mW Charge-Pump PLL With High Spectrum Purity. 113-122 - Liang Fang
A 2.56-GS/s 12-bit 8x-Interleaved ADC With 156.6-dB FoMS in 65-nm CMOS. 123-133 - Zhong Zhang
A Code-Recombination Algorithm-Based ADC With Feature Extraction for WBSN Applications. 134-142 - Jahyun Koo
Low-Noise Distributed RC Oscillator. 143-152 - Shinya Kajiyama
T/R Switch Composed of Three HV-MOSFETs With 12.1-μW Consumption That Enables Per-Channel Self-Loopback AC Tests and -18.1-dB Switching Noise Suppression for 3-D Ultrasound Imaging With 3072-Ch Transceiver. 153-165 - Rohit B. Chaurasiya
Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network. 166-176 - Pietro Nannipieri
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative. 177-186 - Trevor Kroeger
Assessment and Mitigation of Power Side-Channel-Based Cross-PUF Attacks on Arbiter-PUFs and Their Derivatives. 187-200 - Dionysios Filippas
Low-Cost Online Convolution Checksum Checker. 201-212 - Wei Mao
A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing. 213-226 - Zhiqiang Que
Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs. 227-237 - Zunsong Yang
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM. 238-242 - Botao Xiong
Half-Precision Logarithmic Arithmetic Unit Based on the Fused Logarithmic and Antilogarithmic Converter. 243-247 - Yosef Lempel, Rinat Breuer, Joseph Shor
A 700-μm², Ring-Oscillator-Based Thermal Sensor in 16-nm FinFET. 248-252
Volume 30, Number 3, March 2022
- Nakisa Shams
Analysis and Comparison of Low-Power 6-GHz N-Path-Filter-Based Harmonic Selection RF Receiver Front-End Architectures. 253-266 - Jinhai Xiao, Ning Liang, Bingwen Chen, Maliang Liu
An 8.55-17.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fsrms Jitter and Fast Frequency Hopping. 267-276 - Mahesh Kumar Adimulam
A 12-bit, 1.1-GS/s, Low-Power Flash ADC. 277-290 - Zhen Gao
Soft Error Tolerant Convolutional Neural Networks on FPGAs With Ensemble Learning. 291-302 - Kasem Khalil
Designing Novel AAD Pooling in Hardware for a Convolutional Neural Network Accelerator. 303-314 - Hamidreza Esmaeili Taheri
A Pre-Activation, Golden IC Free, Hardware Trojan Detection Approach. 315-324 - Shuo Yang
Golden-Free Hardware Trojan Detection Using Self-Referencing. 325-338 - Divya Praneetha Ravipati
FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies. 339-352
Volume 30, Number 4, April 2022
- Leilei Jin
A Fast Cross-Layer Dynamic Power Estimation Method by Tracking Cycle-Accurate Activity Factors With Spark Streaming. 353-364 - Sandeep Krishna Thirumala, Arnab Raha
Exploring the Design of Energy-Efficient Intermittently Powered Systems Using Reconfigurable Ferroelectric Transistors. 365-378 - Yewei Zhang, Kejie Huang
An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping. 379-391 - Mengyun Liu
Online Fault Detection in ReRAM-Based Computing Systems for Inferencing. 392-405 - Laxmeesha Somappa
Continuous-Time Hybrid ΔΣ Modulators for Sub-μW Power Multichannel Biomedical Applications. 406-417 - Dawen Xu, Zhuangyu Feng
Taming Process Variations in CNFET for Efficient Last-Level Cache Design. 418-431 - Rongmei Chen
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization. 432-439 - Rongmei Chen
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization. 440-448 - Atul Prasad Deb Nath
SoCCom: Automated Synthesis of System-on-Chip Architectures. 449-462 - Yi Tan
Optimization of Gate Voltage in Capacitive DC-DC Converters for Thermoelectric Energy Harvesting. 463-473 - Rui Yao, Yinhua Zhao
Fast Search and Efficient Placement Algorithm for Reconfigurable Tasks on Modern Heterogeneous FPGAs. 474-487 - Mesala M. Sravani
On Efficiency Enhancement of SHA-3 for FPGA-Based Multimodal Biometric Authentication. 488-501 - Weixiong Jiang
FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA. 502-514 - Hassan Salmani
Gradual-N-Justification (GNJ) to Reduce False-Positive Hardware Trojan Detection in Gate-Level Netlist. 515-525 - Eslam Elmitwalli
Machine Learning Attack Resistant Area-Efficient Reconfigurable Ising-PUF. 526-538 - Abdullah Ibn Abbas
A Receiver Front-End for VCSEL-Based Optical Links With 49 UI Turn-On Time. 539-543 - Fei Lyu
High-Throughput Low-Latency Pipelined Divider for Single-Precision Floating-Point Numbers. 544-548 - Erfan Bank Tavakoli
RPkNN: An OpenCL-Based FPGA Implementation of the Dimensionality-Reduced kNN Algorithm Using Random Projection. 549-552
Volume 30, Number 5, May 2022
- Dayane Reis
IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption. 553-565 - Yue Zhao
Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing. 566-578 - Dai Li
MeNTT: A Compact and Efficient Processing-in-Memory Number Theoretic Transform (NTT) Accelerator. 579-588 - Hayssam El-Razouk
Input-Latency Free Versatile Bit-Serial GF(2m) Polynomial Basis Multiplication. 589-602 - Madhan Thirumoorthi
An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic. 603-614 - Sandeep Goyal
A True Full-Duplex IO (TFD-IO) With Background SI Cancellation for High-Density Interfaces. 615-624 - Yulang Feng
A 5-GS/s 6-Bit 15.07-mW Flash ADC With Partially Active Second-Stage Comparison and 2× Time-Domain Interpolation. 625-633 - Yan-Ting Chen
A 12-14.5-GHz 10.2-mW -249-dB FoM Fractional-N Subsampling PLL With a High-Linearity Phase Interpolator in 40-nm CMOS. 634-643 - Qihui Zhang
A 12-Bit Two-Step Single-Slope ADC With a Constant Input-Common-Mode Level Resistor Ramp Generator. 644-655 - Yuhao Chen
Stochastic Computing Using Amplitude and Frequency Encoding. 656-660 - Hesheng Lin
84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor. 661-665 - Shatadal Chatterjee
A Self-Calibration Method of a Pipeline ADC Based on Dynamic Capacitance Allotment. 666-670 - Biswabandhu Jana
A Single-Chip Solution for Diagnosing Peripheral Arterial Disease. 671-675 - Yuting Chen, Yuxuan Nie, Hailong Jiao
An Ultralow-Power 65-nm Standard Cell Library for Near/Subthreshold Digital Circuits. 676-680
Volume 30, Number 6, June 2022
- Syed Mohsin Abbas
High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND. 681-693 - Yiming Yu, Dong Chen, Xiaoning Zhang
A Ku-Band Eight-Element Phased-Array Transmitter With Built-in Self-Test Capability in 180-nm CMOS Technology. 694-705 - Yao Li
A 1.15-mW Low-Power Low-Complexity Reconfigurable FM-UWB Transmitter. 706-719 - Naina Singhal
A 25-30-GHz RMS Error-Minimized 360° Continuous Analog Phase Shifter Using Closed-Loop Self-Tuning I/Q Generator. 720-731 - Xiaolong Liu
Analysis and Design of Magnetically Tuned W -Band Oscillators. 732-743 - Ningcheng Gaoding
A 4th-Order 4-Bit Continuous-Time ΔΣ ADC Based on Active-Passive Integrators With a Resistance Feedback DAC. 744-754 - Souvik Kundu
Memristors Enabled Computing Correlation Parameter In-Memory System: A Potential Alternative to Von Neumann Architecture. 755-768 - Jian Chen
A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations. 769-780 - Hayoung Lee
ECMO: ECC Architecture Reusing Content-Addressable Memories for Obtaining High Reliability in DRAM. 781-793 - Ausmita Sarker
Efficient Error Detection Architectures for Postquantum Signature Falcon's Sampler and KEM SABER. 794-802 - Ziying Ni
A High-Performance SIKE Hardware Accelerator. 803-815 - Kuo-Wei Chang
A Real-Time 1280 × 720 Object Detection Chip With 585 MB/s Memory Traffic. 816-825 - Sina Ghaffari
A Fully Pipelined FPGA Architecture for Multiscale BRISK Descriptors With a Novel Hardware-Aware Sampling Pattern. 826-839 - Youngwoo Ji, Jae-Yoon Sim
A 20.5-nW Resistor-Less Bandgap Voltage Reference With Self-Biased Compensation for Process Variations. 840-843 - Mohamadreza Zolfagharinejad, Mehdi Kamal
Posit Process Element for Using in Energy-Efficient DNN Accelerators. 844-848
Volume 30, Number 7, July 2022
- Yuyang Li, Yawen Wu
Energy-Aware Adaptive Multi-Exit Neural Network Inference Implementation for a Millimeter-Scale Sensing System. 849-859 - Paria Darbani
RASHT: A Partially Reconfigurable Architecture for Efficient Implementation of CNNs. 860-868 - Khaled Alhaj Ali
MOL-Based In-Memory Computing of Binary Neural Networks. 869-880 - Kashif Inayat
Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration. 881-892 - Daney Alex, Vinay Chakravarthi Gogineni
Novel VLSI Architecture for Fractional-Order Correntropy Adaptive Filtering Algorithm. 893-904 - Yao-Hung Tsai
A 0.0067-mm2 12-bit 20-MS/s SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS. 905-914 - Dong-Hyun Yoon
A 3.2-GHz 178-fsrms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier. 915-925 - Hammond Pearce
Detecting Hardware Trojans in PCBs Using Side Channel Loopbacks. 926-937 - Kerem Arikan, Alessandro Palumbo
Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches. 938-951 - Subodha Charles
Digital Watermarking for Detecting Malicious Intellectual Property Cores in NoC Architectures. 952-965 - Feng Qiu
A Simplified Vector-Sum Phase Shifter Topology With Low Noise Figure and High Voltage Gain. 966-974 - Shuo-Wen Chang, Yu-Teng Nien
Test Methodology for Defect-Based Bridge Faults. 975-988 - Fengjuan Wang
A Miniaturized Wideband Interdigital Bandpass Filter With High Out-Band Suppression Based on TSV Technology for W-Band Application. 989-992
Volume 30, Number 8, August 2022
- Yang Su
A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication. 993-1006 - Dongdong Xu
A More Accurate and Robust Binary Ring-LWE Decryption Scheme and Its Hardware Implementation for IoT Devices. 1007-1019 - Rahul Sharma, Rahul Shrestha
Low-Latency and Reconfigurable VLSI-Architectures for Computing Eigenvalues and Eigenvectors Using CORDIC-Based Parallel Jacobi Method. 1020-1033 - Jinming Lu
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration. 1034-1046 - Yichuan Bai
An Efficient High-Throughput Structured-Light Depth Engine. 1047-1058 - Chung-Kuan Cheng
Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis. 1059-1072 - Naveen Kumar Macha
Crosstalk-Computing-Based Gate-Level Reconfigurable Circuits. 1073-1083 - Baver Ozceylan
Minimizing the Maximum Processor Temperature by Temperature-Aware Scheduling of Real-Time Tasks. 1084-1097 - Fereshteh Kalantari
Hardware-Efficient, On-the-Fly, On-Implant Spike Sorter Dedicated to Brain-Implantable Microsystems. 1098-1106 - Wei Xiong
3-D Compact Marchand Balun Design Based on Through-Silicon via Technology for Monolithic and 3-D Integration. 1107-1118 - Yu-Hsuan Lee
A Design of 12.8-Gpixels/s Hardware-Efficient Lossless Embedded Compression Engine for Video Coding Applications. 1119-1132
Volume 30, Number 9, September 2022
- Xuecheng Wang
Design of a Real-Time Movement Decomposition-Based Rodent Tracker and Behavioral Analyzer Based on FPGA. 1133-1143 - Jun-Sheng Ng
A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks. 1144-1157 - Tengfei Wang
Efficient Implementation of Dilithium Signature Scheme on FPGA SoC Platform. 1158-1171 - Sina Sayyah Ensan
Addressing Resiliency of In-Memory Floating Point Computation. 1172-1183 - Yu-Hsiang Chiang, Tian-Sheuan Chang
A 14 μJ/Decision Keyword-Spotting Accelerator With In-SRAMComputing and On-Chip Learning for Customization. 1184-1192 - Zihao Xuan
High-Efficiency Data Conversion Interface for Reconfigurable Function-in-Memory Computing. 1193-1206 - Nitin Pundir
Power Side-Channel Leakage Assessment Framework at Register-Transfer Level. 1207-1218 - Arijit Nath
Pop-Crypt: Identification and Management of Popular Words for Enhancing Lifetime of EnCrypted Nonvolatile Main Memories. 1219-1229 - Theodros Nigussie
Design Obfuscation Through 3-D Split Fabrication With Smart Partitioning. 1230-1243 - Frank T. Werner
Detection of Recycled ICs Using Backscattering Side-Channel Analysis. 1244-1255 - Yale Wang
A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs. 1256-1268 - Youngmin Park
A 270-mA Self-Calibrating-Clocked Output-Capacitor-Free LDO With 0.15-1.15V Output Range and 0.183-fs FoM. 1269-1280 - Indranil Bhattacharjee
A 0.3 nW, 0.093%/V Line Sensitivity, Temperature Compensated Bulk-Programmable Voltage Reference for Wireless Sensor Nodes. 1281-1293 - S. Babak Hamidi
A New Pathway Toward Implementing a Fully Integrated Band-Switchable CMOS Power Amplifier Utilizing Bit Optimized Reconfigurable Network (BORN). 1294-1305 - Xiaorui Zhu
Analysis and Design of a DC-12-GHz Distribution Power Amplifier for Quantum Key Distribution Application. 1306-1318 - Hamed Nasiri
Ultra-Low Power SAR ADC Using Statistical Characteristics of Low-Activity Signals. 1319-1331 - Smrutilekha Samanta
A Pairwise Swap Enabled Randomized DEM Addressing Intersegment Mismatch for Current Steering Digital-to-Analog Converters. 1332-1340 - Aaron C.-W. Liang
A General and Automatic Cell Layout Generation Framework With Implicit Learning on Design Rules. 1341-1354 - Sai Pentapati
Metal Layer Sharing: A Routing Optimization Technique for Monolithic 3D ICs. 1355-1367 - Yuxing Chen
An Efficient Reconfigurable Encoder for the IEEE 1901 Standard. 1368-1372
Volume 30, Number 10, October 2022
- Andrei A. Antonov
Power-On Reset Circuit in 180-nm CMOS With Brownout Detection, Stable Switching Points, Long Reset Pulse Duration, and Resilience to Switching Noise. 1373-1380 - Young-Ha Hwang
A Fully Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques. 1381-1390 - Xingyuan Tong
A 12-Bit Current-Steering DAC With Unary- Splitting -Binary Segmented Architecture and Improved Decoding Circuit Topology. 1391-1400 - Rozhin Yasaei
Golden Reference-Free Hardware Trojan Localization Using Graph Convolutional Network. 1401-1411 - Mahmudul Hasan
Trojan Resilient Computing in COTS Processors Under Zero Trust. 1412-1424 - Qinyu Chen
Cerebron: A Reconfigurable Architecture for Spatiotemporal Sparse Spiking Neural Networks. 1425-1437 - Arash Fouman Ajirlou
NoD: A Neural Network-Over-Decoder for Edge Intelligence. 1438-1447 - Chun Tao
On Noise Stability and Robustness of Adversarially Trained Networks on NVM Crossbars. 1448-1460 - Inho Lee
Dynamic Rate Neural Acceleration Using Multiprocessing Mode Support. 1461-1472 - Prasanna Kumar Saragada
In-Memory Computation With Improved Linearity Using Adaptive Sparsity-Based Compact Thermometric Code. 1473-1483 - Eleni Maragkoudaki
Energy-Efficient Encoding for High-Speed Serial Interfaces. 1484-1496 - Giuliano Sisto
Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era. 1497-1506 - Zhen Wang
Accurate Reliability Boundary Evaluation of Approximate Arithmetic Circuit. 1507-1518 - Jin-Tai Yan
Fixed-Order Placement of Pipelined Architecture in Rapid Single-Flux-Quantum Circuits. 1519-1532 - Alexander Choo Chia Chun
A Reconfigurable CMOS Rectifier With 14-dB Power Dynamic Range Achieving >36-dB/mm2 FoM for RF-Based Hybrid Energy Harvesting. 1533-1537 - Jacob Atkinson
Systematic Design of Loop Circuit Topologies Using C/IDS Methodology. 1538-1542 - Irith Pomeranz
Preponing Fault Detections for Test Compaction Under Transparent Scan. 1543-1547 - Abolfazl Zokaei
Memory Optimized Hardware Implementation of Open FEC Encoder. 1548-1552 - Suwen Song
A Universal Efficient Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders. 1553-1557 - Dengquan Li
A Fast Convergence Second-Order Compensation for Timing Skew in Time-Interleaved ADCs. 1558-1562 - Zhenshan Xie
Low-Latency Nested Decoding for Short Generalized Integrated Interleaved BCH Codes. 1563-1567 - Irith Pomeranz
Test Sequences for Faults in the Scan Logic. 1568-1572
Volume 30, Number 11, November 2022
- Chao Fang
An Algorithm-Hardware Co-Optimized Framework for Accelerating N: M Sparse Transformers. 1573-1586 - Shengzhao Li
An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs. 1587-1600 - Abhishek Ramdas Nair
Multiplierless MP-Kernel Machine for Energy-Efficient Edge Devices. 1601-1614 - Mustafa Fayez Ali
Compute-in-Memory Technologies and Architectures for Deep Learning Workloads. 1615-1630 - Yisong Kuang
ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator. 1631-1641 - Wenzhe Guo
Efficient Neuromorphic Hardware Through Spiking Temporal Online Local Learning. 1642-1653 - Krithika Dhananjay
High Bandwidth Thermal Covert Channel in 3-D-Integrated Multicore Processors. 1654-1667 - Sankatali Venkateswarlu
Thermal Performance Analysis of Mempool RISC-V Multicore SoC. 1668-1676 - Ying Zhang
BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature. 1677-1690 - Xiao Hu
Efficient Homomorphic Convolution Designs on FPGA for Secure Inference. 1691-1704 - Kleber Stangherlin
Design and Implementation of a Secure RISC-V Microprocessor. 1705-1715 - Seyed Hamidreza Moghadas
ROPAD: Enhancing the Digital Ring Oscillator Probing Attempt Detector for Protecting Irregular Data Buses. 1716-1727 - Hyunho Park
Self-Shut-Off Pulsed Latches for Minimizing Sequencing Overhead. 1728-1738 - Fabian Khateb
A 0.5-V Multiple-Input Bulk-Driven OTA in 0.18-μm CMOS. 1739-1747 - Hesheng Lin
Efficient Backside Power Delivery for High-Performance Computing Systems. 1748-1756 - Ji-Yung Lin
Multitimescale Mitigation for Performance Variability Improvement in Time-Critical Systems. 1757-1769 - Xiaoyang Ma
CapCAM: A Multilevel Capacitive Content Addressable Memory for High-Accuracy and High-Scalability Search and Compute Applications. 1770-1782 - Jai-Ming Lin
PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability. 1783-1793 - Mubeen Zafar, Muhammad Naeem Awais, Muhammad Naeem Shehzad, Abbas Javed
CEVGMM: Computationally Efficient Versatile Generic Memristor Model. 1794-1802 - Irith Pomeranz
Functional Test Sequences as a Source for Partially Functional Launch-on-Shift Tests. 1803-1807 - Wen Xun Lian
A -20-dBm Sensitivity RF Energy-Harvesting Rectifier Front End Using a Transformer IMN. 1808-1812
Volume 30, Number 12, December 2022
- Zhen Li
Adaptable Approximate Multiplier Design Based on Input Distribution and Polarity. 1813-1826 - Zhufei Chu
Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits. 1827-1839 - Hsi-Hung Lu
Configurable Independent Component Analysis Preprocessing Accelerator. 1840-1852 - Zhe-Yu Wang, Pei-Yun Tsai
Design and Implementation of a 6.5-Gb/s Multiradix Simplified Viterbi-Sphere Decoder for Trellis-Coded Generalized Spatial Modulation With Spatial Multiplexing. 1853-1866 - Zhongyang Liu
A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch Design. 1867-1877 - Wei Mao
An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks. 1878-1890 - Md. Najrul Islam
An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks. 1891-1901 - Chen Yang
A Sparse CNN Accelerator for Eliminating Redundant Computations in Intra- and Inter-Convolutional/Pooling Layers. 1902-1915 - Muhammad Rizwan Khan
A 380-μW Electrochemical Impedance Measurement System for Protein Sensing. 1916-1927 - Hanrui Zhang
A 2.5-MHz BW, 75-dB SNDR Noise-Shaping SAR ADC With a 1st-Order Hybrid EF-CIFF Structure Assisted by Unity-Gain Buffer. 1928-1932
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