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Mirko Loghi
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2020 – today
- 2024
- [j12]Riccardo Fontanini
, Alessandro Pilotto
Reducing the spike rate of deep spiking neural networks based on time-encoding. Neuromorph. Comput. Eng. 4(3): 34004 (2024) - 2023
- [c23]Marco Massarotto
Adiabatic Spiking Neurons and Synapses for Ultra-Low Energy Neuromorphic Computing. ICECS 2023: 1-4 - 2022
- [c22]Riccardo Fontanini, David Esseni, Mirko Loghi:
Reducing the Spike Rate in Deep Spiking Neural Networks. ICONS 2022: 8:1-8:8 - 2021
- [i2]Riccardo Fontanini, Marco Massarotto, Ruben Specogna, Francesco Driussi, Mirko Loghi, David Esseni:
Modelling and design of FTJs as high reading-impedance synaptic devices. CoRR abs/2105.00752 (2021) - [i1]David Esseni, Riccardo Fontanini, Daniel Lizzit, Marco Massarotto, Francesco Driussi, Mirko Loghi:
Ferroelectric based FETs and synaptic devices for highly energy efficient computational technologies. CoRR abs/2105.00864 (2021)
2010 – 2019
- 2018
- [j11]Alexander Rudolf Ganis
A Portable 3-D Imaging FMCW MIMO Radar Demonstrator With a $24\times 24$ Antenna Array for Medium-Range Applications. IEEE Trans. Geosci. Remote. Sens. 56(1): 298-312 (2018) - 2014
- [j10]Andrea Calimera
Dynamic Indexing: Leakage-Aging Co-Optimization for Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 251-264 (2014) - [j9]Haroon Mahmood
Energy/Lifetime Cooptimization by Cache Partitioning With Graceful Performance Degradation. IEEE Trans. Very Large Scale Integr. Syst. 22(8): 1705-1715 (2014) - 2013
- [c21]Stefan Wieser, Pier Luca Montessoro, Mirko Loghi:
Firefly-Inspired Synchronization of Sensor Networks with Variable Period Lengths. ICANNGA 2013: 376-385 - 2012
- [c20]Haroon Mahmood
Application-specific memory partitioning for joint energy and lifetime optimization. DATE 2012: 364-369 - [c19]Mirko Loghi, Haroon Mahmood
Energy-optimal caches with guaranteed lifetime. ISLPED 2012: 141-146 - [c18]Haroon Mahmood
Aging-aware caches with graceful degradation of performance. VLSI-SoC 2012: 237-242 - 2011
- [c17]Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino:
Partitioned cache architectures for reduced NBTI-induced aging. DATE 2011: 938-943 - [c16]Andrea Calimera
Buffering of frequent accesses for reduced cache aging. ACM Great Lakes Symposium on VLSI 2011: 295-300 - 2010
- [j8]Mirko Loghi, Olga Golubeva, Enrico Macii, Massimo Poncino:
Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Subbanking. IEEE Trans. Computers 59(7): 891-904 (2010) - [c15]Andrea Calimera
Aging effects of leakage optimizations for caches. ACM Great Lakes Symposium on VLSI 2010: 95-98 - [c14]Andrea Calimera
Dynamic indexing: concurrent leakage and aging optimization for caches. ISLPED 2010: 343-348
2000 – 2009
- 2009
- [j7]Franco Fummi, Mirko Loghi, Massimo Poncino, Graziano Pravadelli
A cosimulation methodology for HW/SW validation and performance estimation. ACM Trans. Design Autom. Electr. Syst. 14(2): 23:1-23:32 (2009) - [j6]Mirko Loghi, Paolo Azzoni, Massimo Poncino:
Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching. IEEE Trans. Very Large Scale Integr. Syst. 17(5): 728-732 (2009) - [c13]Cesare Ferri, R. Iris Bahar
Energy-optimal synchronization primitives for single-chip multi-processors. ACM Great Lakes Symposium on VLSI 2009: 141-144 - 2007
- [j5]Franco Fummi, Mirko Loghi, Giovanni Perbellini, Massimo Poncino:
SystemC co-simulation for core-based embedded systems. Des. Autom. Embed. Syst. 11(2-3): 141-166 (2007) - [j4]Francesco Poletti, Antonio Poggiali, Davide Bertozzi, Luca Benini
Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support. IEEE Trans. Computers 56(5): 606-621 (2007) - [j3]Mirko Loghi, Luca Benini
Power macromodeling of MPSoC message passing primitives. ACM Trans. Embed. Comput. Syst. 6(4): 31 (2007) - [c12]Olga Golubeva, Mirko Loghi, Massimo Poncino, Enrico Macii:
Architectural leakage-aware management of partitioned scratchpad memories. DATE 2007: 1665-1670 - [c11]Olga Golubeva, Mirko Loghi, Massimo Poncino:
On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessors. ACM Great Lakes Symposium on VLSI 2007: 489-492 - [c10]Olga Golubeva, Mirko Loghi, Enrico Macii, Massimo Poncino:
Locality-driven architectural cache sub-banking for leakage energy reduction. ISLPED 2007: 274-279 - 2006
- [j2]Mirko Loghi, Massimo Poncino, Luca Benini
Cache coherence tradeoffs in shared-memory MPSoCs. ACM Trans. Embed. Comput. Syst. 5(2): 383-407 (2006) - [c9]Franco Fummi, Giovanni Perbellini, Mirko Loghi, Massimo Poncino:
ISS-centric modular HW/SW co-simulation. ACM Great Lakes Symposium on VLSI 2006: 31-36 - [c8]Mirko Loghi, Massimo Poncino, Luca Benini
Synchronization-driven dynamic speed scaling for MPSoCs. ISLPED 2006: 346-349 - 2005
- [j1]Mirko Loghi, Tiziana Margaria
Dynamic and Formal Verification of Embedded Systems: A Comparative Survey. Int. J. Parallel Program. 33(6): 585-611 (2005) - [c7]Mirko Loghi, Massimo Poncino:
Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions. DATE 2005: 508-513 - [c6]Mirko Loghi, Paolo Azzoni, Massimo Poncino:
Tag Overflow Buffering: An Energy-Efficient Cache Architecture. DATE 2005: 520-525 - [c5]Franco Fummi, Mirko Loghi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino:
Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation. DATE 2005: 798-803 - [c4]Mirko Loghi, Martin Letis, Luca Benini, Massimo Poncino:
Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors. ACM Great Lakes Symposium on VLSI 2005: 276-281 - 2004
- [c3]Mirko Loghi, Federico Angiolini, Davide Bertozzi, Luca Benini
Analyzing On-Chip Communication in a MPSoC Environment. DATE 2004: 752-757 - [c2]Mirko Loghi, Massimo Poncino, Luca Benini:
Cycle-accurate power analysis for multiprocessor systems-on-a-chip. ACM Great Lakes Symposium on VLSI 2004: 410-406 - [c1]Mirko Loghi, Luca Benini, Massimo Poncino:
Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor. ICCD 2004: 393-396
Coauthor Index
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