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Massimo Poncino
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2020 – today
- 2025
- [i32]Francesco Daghero, Daniele Jahier Pagliari, Francesco Conti, Luca Benini, Massimo Poncino, Alessio Burrello:
Lightweight Software Kernels and Hardware Extensions for Efficient Sparse Deep Neural Networks on Microcontrollers. CoRR abs/2503.06183 (2025) - 2024
- [j96]Francesco Daghero
, Alessio Burrello
Dynamic Decision Tree Ensembles for Energy-Efficient Inference on IoT Edge Nodes. IEEE Internet Things J. 11(1): 742-757 (2024) - [c237]Alessio Burrello, Francesco Carlucci, Giovanni Pollo
Optimization and Deployment of Deep Neural Networks for PPG-based Blood Pressure Estimation Targeting Low-power Wearables. BioCAS 2024: 1-5 - [c236]Mohamed Amine Hamdi
Integrating SystemC-AMS Power Modeling with a RISC-V ISS for Virtual Prototyping of Battery-operated Embedded Devices. CF (Companion) 2024 - [c235]Khaled Alamin, Daniele Jahier Pagliari, Yukai Chen, Enrico Macii, Sara Vinco, Massimo Poncino:
Model-Driven Feature Engineering for Data-Driven Battery SOH Model. DATE 2024: 1-6 - [c234]Matteo Risso, Chen Xie, Francesco Daghero, Alessio Burrello, Seyedmorteza Mollaei, Marco Castellano, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari:
HW-SW Optimization of DNNs for Privacy-Preserving People Counting on Low-Resolution Infrared Arrays. DATE 2024: 1-6 - [c233]Matteo Risso, Francesco Daghero, Beatrice Alessandra Motetti, Daniele Jahier Pagliari, Enrico Macii, Massimo Poncino, Alessio Burrello:
Optimized Deployment of Deep Neural Networks for Visual Pose Estimation on Nano-drones. ERF (1) 2024: 304-309 - [c232]Francesco Daghero
Accelerating Depthwise Separable Convolutions on Ultra-Low-Power Devices. SAMOS 2024: 46-58 - [i31]Matteo Risso, Chen Xie, Francesco Daghero, Alessio Burrello, Seyedmorteza Mollaei, Marco Castellano, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari:
HW-SW Optimization of DNNs for Privacy-preserving People Counting on Low-resolution Infrared Arrays. CoRR abs/2402.01226 (2024) - [i30]Matteo Risso, Francesco Daghero, Beatrice Alessandra Motetti, Daniele Jahier Pagliari, Enrico Macii, Massimo Poncino, Alessio Burrello:
Optimized Deployment of Deep Neural Networks for Visual Pose Estimation on Nano-drones. CoRR abs/2402.15273 (2024) - [i29]Mohamed Amine Hamdi, Giovanni Pollo, Matteo Risso, Germain Haugou, Alessio Burrello, Enrico Macii, Massimo Poncino, Sara Vinco, Daniele Jahier Pagliari:
Integrating SystemC-AMS Power Modeling with a RISC-V ISS for Virtual Prototyping of Battery-operated Embedded Devices. CoRR abs/2404.01861 (2024) - [i28]Luca Benfenati, Daniele Jahier Pagliari, Luca Zanatta, Yhorman Alexander Bedoya Velez, Andrea Acquaviva, Massimo Poncino, Enrico Macii, Luca Benini, Alessio Burrello:
Foundation Models for Structural Health Monitoring. CoRR abs/2404.02944 (2024) - [i27]Francesco Daghero, Alessio Burrello, Massimo Poncino, Enrico Macii, Daniele Jahier Pagliari:
Accelerating Depthwise Separable Convolutions on Ultra-Low-Power Devices. CoRR abs/2406.12478 (2024) - [i26]Beatrice Alessandra Motetti, Matteo Risso, Alessio Burrello, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari:
Joint Pruning and Channel-wise Mixed-Precision Quantization for Efficient Deep Neural Networks. CoRR abs/2407.01054 (2024) - [i25]Alessio Burrello, Francesco Carlucci
Optimization and Deployment of Deep Neural Networks for PPG-based Blood Pressure Estimation Targeting Low-power Wearables. CoRR abs/2409.07485 (2024) - [i24]Matteo Risso, Alessia Goffi, Beatrice Alessandra Motetti, Alessio Burrello, Jean Baptiste Bove, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari, Giuseppe Maffeis:
Building Damage Assessment in Conflict Zones: A Deep Learning Approach Using Geospatial Sub-Meter Resolution Data. CoRR abs/2410.04802 (2024) - [i23]Giovanni Pollo, Alessio Burrello, Enrico Macii, Massimo Poncino, Sara Vinco, Daniele Jahier Pagliari:
Coupling Neural Networks and Physics Equations For Li-Ion Battery State-of-Charge Prediction. CoRR abs/2412.16724 (2024) - [i22]Luca Benfenati, Sofia Belloni, Alessio Burrello, Panagiotis Kasnesis, Xiaying Wang, Luca Benini, Massimo Poncino, Enrico Macii, Daniele Jahier Pagliari:
EnhancePPG: Improving PPG-based Heart Rate Estimation with Self-Supervision and Augmentation. CoRR abs/2412.17860 (2024) - 2023
- [j95]Chen Xie
Efficient Deep Learning Models for Privacy-Preserving People Counting on Low-Resolution Infrared Arrays. IEEE Internet Things J. 10(15): 13895-13907 (2023) - [j94]Chen Xie
Reducing the Energy Consumption of sEMG-Based Gesture Recognition at the Edge Using Transformers and Dynamic Inference. Sensors 23(4): 2065 (2023) - [j93]Matteo Orlando
A Framework for Economic and Environmental Benefit Through Renewable Energy Community. IEEE Syst. J. 17(4): 5626-5635 (2023) - [j92]Matteo Risso
Lightweight Neural Architecture Search for Temporal Convolutional Networks at the Edge. IEEE Trans. Computers 72(3): 744-758 (2023) - [j91]Young Hoo Cho, Donkyu Baek
Multi-Criteria Coordinated Electric Vehicle-Drone Hybrid Delivery Service Planning. IEEE Trans. Veh. Technol. 72(5): 5892-5905 (2023) - [c231]Alessio Burrello, Matteo Risso, Noemi Tomasello, Yukai Chen, Luca Benini, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
Energy-efficient Wearable-to-Mobile Offload of ML Inference for PPG-based Heart-Rate Estimation. DATE 2023: 1-6 - [c230]Khaled Sidahmed Sidahmed Alamin
Model-Driven Dataset Generation for Data-Driven Battery SOH Models. ISLPED 2023: 1-6 - [c229]Matteo Risso, Alessio Burrello, Giuseppe Maria Sarda
Precision-aware Latency and Energy Balancing on Multi-Accelerator Platforms for DNN Inference. ISLPED 2023: 1-6 - [i21]Matteo Risso, Alessio Burrello
Lightweight Neural Architecture Search for Temporal Convolutional Networks at the Edge. CoRR abs/2301.10281 (2023) - [i20]Chen Xie, Francesco Daghero, Yukai Chen, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari:
Efficient Deep Learning Models for Privacy-preserving People Counting on Low-resolution Infrared Arrays. CoRR abs/2304.06059 (2023) - [i19]Matteo Risso, Alessio Burrello, Giuseppe Maria Sarda, Luca Benini, Enrico Macii, Massimo Poncino, Marian Verhelst, Daniele Jahier Pagliari:
Precision-aware Latency and Energy Balancing on Multi-Accelerator Platforms for DNN Inference. CoRR abs/2306.05060 (2023) - [i18]Alessio Burrello, Matteo Risso, Noemi Tomasello, Yukai Chen, Luca Benini, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari:
Energy-efficient Wearable-to-Mobile Offload of ML Inference for PPG-based Heart-Rate Estimation. CoRR abs/2306.06129 (2023) - [i17]Francesco Daghero, Alessio Burrello, Enrico Macii, Paolo Montuschi, Massimo Poncino, Daniele Jahier Pagliari:
Dynamic Decision Tree Ensembles for Energy-Efficient Inference on IoT Edge Nodes. CoRR abs/2306.09789 (2023) - 2022
- [j90]Alessio Burrello
Embedding Temporal Convolutional Networks for Energy-efficient PPG-based Heart Rate Monitoring. ACM Trans. Comput. Heal. 3(2): 19:1-19:25 (2022) - [j89]Matteo Orlando
A Smart Meter Infrastructure for Smart Grid IoT Applications. IEEE Internet Things J. 9(14): 12529-12541 (2022) - [j88]Alessio Burrello
Traffic Load Estimation from Structural Health Monitoring sensors using supervised learning. Sustain. Comput. Informatics Syst. 35: 100704 (2022) - [j87]Francesco Daghero
Human Activity Recognition on Microcontrollers with Quantized and Adaptive Deep Neural Networks. ACM Trans. Embed. Comput. Syst. 21(4): 46:1-46:28 (2022) - [j86]Nicola Dall'Ora
Digital Transformation of a Production Line: Network Design, Online Data Collection and Energy Monitoring. IEEE Trans. Emerg. Top. Comput. 10(1): 46-59 (2022) - [c228]Alessio Burrello
Improving PPG-based Heart-Rate Monitoring with Synthetically Generated Data. BioCAS 2022: 153-157 - [c227]Khaled Sidahmed Sidahmed Alamin
A Machine Learning-based Digital Twin for Electric Vehicle Battery Modeling. COINS 2022: 1-6 - [c226]Alessio Burrello
Bioformers: Embedding Transformers for Ultra-Low Power sEMG-based Gesture Recognition. DATE 2022: 1443-1448 - [c225]Davide Cannizzaro, Filomena Simone, Klaus Illgner-Fehns, Sara Mata, Ivan Mondino, Alberto Ghiazza, Massimo Poncino, Santa Di Cataldo:
Quality inspection of critical aircraft engine components: towards full automation. ETFA 2022: 1-4 - [c224]Matteo Risso, Alessio Burrello
Channel-wise Mixed-precision Assignment for DNN Inference on Constrained Edge Nodes. IGSC 2022: 1-6 - [c223]Chen Xie, Francesco Daghero
Privacy-preserving Social Distance Monitoring on Microcontrollers with Low-Resolution Infrared Sensors and CNNs. ISCAS 2022: 1332-1336 - [c222]Yukai Chen
C-NMT: A Collaborative Inference Framework for Neural Machine Translation. ISCAS 2022: 1512-1516 - [c221]Matteo Risso, Alessio Burrello
Multi-Complexity-Loss DNAS for Energy-Efficient and Memory-Constrained Deep Neural Networks. ISLPED 2022: 28:1-28:6 - [c220]Francesco Daghero
Two-stage Human Activity Recognition on Microcontrollers with Decision Trees and CNNs. PRIME 2022: 173-176 - [i16]Alessio Burrello, Daniele Jahier Pagliari, Pierangelo Maria Rapa, Matilde Semilia, Matteo Risso, Tommaso Polonelli, Massimo Poncino, Luca Benini, Simone Benatti
Embedding Temporal Convolutional Networks for Energy-Efficient PPG-Based Heart Rate Monitoring. CoRR abs/2203.04396 (2022) - [i15]Alessio Burrello, Alberto Dequino, Daniele Jahier Pagliari, Francesco Conti, Marcello Zanghieri, Enrico Macii, Luca Benini, Massimo Poncino:
TCN Mapping Optimization for Ultra-Low Power Time-Series Edge Inference. CoRR abs/2203.12925 (2022) - [i14]Alessio Burrello, Francesco Bianco Morghet, Moritz Scherer, Simone Benatti
Bioformers: Embedding Transformers for Ultra-Low Power sEMG-based Gesture Recognition. CoRR abs/2203.12932 (2022) - [i13]Matteo Risso, Alessio Burrello, Daniele Jahier Pagliari, Francesco Conti, Lorenzo Lamberti, Enrico Macii, Luca Benini, Massimo Poncino:
Pruning In Time (PIT): A Lightweight Network Architecture Optimizer for Temporal Convolutional Networks. CoRR abs/2203.14768 (2022) - [i12]Alessio Burrello, Daniele Jahier Pagliari, Matteo Risso, Simone Benatti
Q-PPG: Energy-Efficient PPG-based Heart Rate Monitoring on Wearable Devices. CoRR abs/2203.14907 (2022) - [i11]Matteo Risso, Alessio Burrello, Daniele Jahier Pagliari, Simone Benatti
Robust and Energy-efficient PPG-based Heart-Rate Monitoring. CoRR abs/2203.16339 (2022) - [i10]Francesco Daghero, Alessio Burrello, Daniele Jahier Pagliari, Luca Benini, Enrico Macii, Massimo Poncino:
Energy-Efficient Adaptive Machine Learning on IoT End-Nodes With Class-Dependent Confidence. CoRR abs/2204.03431 (2022) - [i9]Yukai Chen, Roberta Chiaro, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari:
C-NMT: A Collaborative Inference Framework for Neural Machine Translation. CoRR abs/2204.04043 (2022) - [i8]Chen Xie, Francesco Daghero, Yukai Chen, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari:
Privacy-preserving Social Distance Monitoring on Microcontrollers with Low-Resolution Infrared Sensors and CNNs. CoRR abs/2204.10541 (2022) - [i7]Francesco Daghero
Ultra-compact Binary Neural Networks for Human Activity Recognition on RISC-V Processors. CoRR abs/2205.12781 (2022) - [i6]Francesco Daghero
Adaptive Random Forests for Energy-Efficient Inference on Microcontrollers. CoRR abs/2205.13838 (2022) - [i5]Matteo Risso, Alessio Burrello
Multi-Complexity-Loss DNAS for Energy-Efficient and Memory-Constrained Deep Neural Networks. CoRR abs/2206.00302 (2022) - [i4]Francesco Daghero
Two-stage Human Activity Recognition on Microcontrollers with Decision Trees and CNNs. CoRR abs/2206.07652 (2022) - [i3]Khaled Sidahmed Sidahmed Alamin
A Machine Learning-based Digital Twin for Electric Vehicle Battery Modeling. CoRR abs/2206.08080 (2022) - [i2]Matteo Risso, Alessio Burrello
Channel-wise Mixed-precision Assignment for DNN Inference on Constrained Edge Nodes. CoRR abs/2206.08852 (2022) - [i1]Francesco Daghero
Human Activity Recognition on Microcontrollers with Quantized and Adaptive Deep Neural Networks. CoRR abs/2209.00839 (2022) - 2021
- [j85]Francesco Daghero
Chapter Eight - Energy-efficient deep learning inference on edge devices. Adv. Comput. 122: 247-301 (2021) - [j84]Tania Cerquitelli
Enhancing manufacturing intelligence through an unsupervised data-driven methodology for cyclic industrial processes. Expert Syst. Appl. 182: 115269 (2021) - [j83]Tania Cerquitelli
Manufacturing as a Data-Driven Practice: Methodologies, Technologies, and Tools. Proc. IEEE 109(4): 399-422 (2021) - [j82]Alessio Burrello
Q-PPG: Energy-Efficient PPG-Based Heart Rate Monitoring on Wearable Devices. IEEE Trans. Biomed. Circuits Syst. 15(6): 1196-1209 (2021) - [j81]Daniele Jahier Pagliari
CRIME: Input-Dependent Collaborative Inference for Recurrent Neural Networks. IEEE Trans. Computers 70(10): 1626-1639 (2021) - [j80]Daniele Jahier Pagliari
Low-Overhead Adaptive Brightness Scaling for Energy Reduction in OLED Displays. IEEE Trans. Emerg. Top. Comput. 9(3): 1625-1636 (2021) - [j79]Yukai Chen
Assessing the Impact of Sensor-Based Task Scheduling on Battery Lifetime in IoT Devices. IEEE Trans. Instrum. Meas. 70: 1-15 (2021) - [j78]Sara Vinco
A Microservices-Based Framework for Smart Design and Optimization of PV Installations. IEEE Trans. Sustain. Comput. 6(4): 531-543 (2021) - [c219]Francesco Daghero
Ultra-compact binary neural networks for human activity recognition on RISC-V processors. CF 2021: 3-11 - [c218]Matteo Orlando
Design of District-level Photovoltaic Installations for Optimal Power Production and Economic Benefit. COMPSAC 2021: 1873-1878 - [c217]Matteo Risso
Pruning In Time (PIT): A Lightweight Network Architecture Optimizer for Temporal Convolutional Networks. DAC 2021: 1015-1020 - [c216]Khaled Alamin
Digital Twin Extension with Extra-Functional Properties. DATE 2021: 434-439 - [c215]Matteo Risso
Robust and Energy-Efficient PPG-Based Heart-Rate Monitoring. ISCAS 2021: 1-5 - [c214]Alessio Burrello
TCN Mapping Optimization for Ultra-Low Power Time-Series Edge Inference. ISLPED 2021: 1-6 - [c213]Chen Xie, Daniele Jahier Pagliari
ACME: An Energy-Efficient Approximate Bus Encoding for I2C. ISLPED 2021: 1-6 - [c212]Francesco Daghero
Adaptive Random Forests for Energy-Efficient Inference on Microcontrollers. VLSI-SoC 2021: 1-6 - [c211]Francesco Daghero
Low-Overhead Early-Stopping Policies for Efficient Random Forests Inference on Microcontrollers. VLSI-SoC (Selected Papers) 2021: 25-47 - 2020
- [j77]Valerio Tenace
Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 397-410 (2020) - [j76]Yukai Chen
Modeling and Simulation of Cyber-Physical Electrical Energy Systems With SystemC-AMS. IEEE Trans. Sustain. Comput. 5(4): 552-567 (2020) - [c210]Matteo Orlando
Optimal Configuration and Placement of PV Systems in Building Roofs with Cost Analysis. COMPSAC 2020: 1411-1416 - [c209]Daniele Jahier Pagliari
Input-Dependent Edge-Cloud Mapping of Recurrent Neural Networks Inference. DAC 2020: 1-6 - [c208]Sara Vinco, Yukai Chen
A Diode-Aware Model of PV Modules from Datasheet Specifications. DATE 2020: 816-821 - [c207]Alessio Burrello
Predicting Hard Disk Failures in Data Centers Using Temporal Convolutional Neural Networks. Euro-Par Workshops 2020: 277-289 - [c206]Francesco Daghero
Energy-Efficient Adaptive Machine Learning on IoT End-Nodes With Class-Dependent Confidence. ICECS 2020: 1-4
2010 – 2019
- 2019
- [j75]Yukai Chen
A SystemC-AMS Framework for the Design and Simulation of Energy Management in Electric Vehicles. IEEE Access 7: 25779-25791 (2019) - [j74]Daniele Jahier Pagliari
Automated Synthesis of Energy-Efficient Reconfigurable-Precision Circuits. IEEE Access 7: 172030-172044 (2019) - [j73]Daniele Jahier Pagliari
Fine-Grain Back Biasing for the Design of Energy-Quality Scalable Operators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1042-1055 (2019) - [j72]Yukai Chen
SystemC-AMS Thermal Modeling for the Co-simulation of Functional and Extra-Functional Properties. ACM Trans. Design Autom. Electr. Syst. 24(1): 4:1-4:26 (2019) - [j71]Sara Vinco
A Cross-level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors. ACM Trans. Design Autom. Electr. Syst. 24(3): 27:1-27:23 (2019) - [j70]Donkyu Baek
Battery-Aware Operation Range Estimation for Terrestrial and Aerial Electric Vehicles. IEEE Trans. Veh. Technol. 68(6): 5471-5482 (2019) - [c205]Daniele Jahier Pagliari
Low-Overhead Power Trace Obfuscation for Smart Meter Privacy. DAC 2019: 111 - [c204]Daniele Jahier Pagliari
Irradiance-Driven Partial Reconfiguration of PV Panels. DATE 2019: 884-889 - [c203]Daniele Jahier Pagliari
Dynamic Beam Width Tuning for Energy-Efficient Recurrent Neural Networks. ACM Great Lakes Symposium on VLSI 2019: 69-74 - [c202]Daniele Jahier Pagliari
Optimal Input-Dependent Edge-Cloud Partitioning for RNN Inference. ICECS 2019: 442-445 - [c201]Yukai Chen
A Semi-Empirical Model of PV Modules Including Manufacturing I-V Mismatch. ICECS 2019: 919-922 - [c200]Donkyu Baek, Yukai Chen
Battery-Aware Electric Truck Delivery Route Planner. ISLPED 2019: 1-6 - [c199]Daniele Jahier Pagliari
CNN-Based Camera-less User Attention Detection for Smartphone Power Management. ISLPED 2019: 1-6 - 2018
- [j69]Alberto Bocca
Composable Battery Model Templates Based on Manufacturers' Data. IEEE Des. Test 35(3): 66-72 (2018) - [j68]Alberto Bocca, Yukai Chen
Aging and Cost Optimal Residential Charging for Plug-In EVs. IEEE Des. Test 35(6): 16-24 (2018) - [j67]Yukai Chen
Empirical derivation of upper and lower bounds of NBTI aging for embedded cores. Microelectron. Reliab. 80: 294-305 (2018) - [j66]Daniele Jahier Pagliari
LAPSE: Low-Overhead Adaptive Power Saving and Contrast Enhancement for OLEDs. IEEE Trans. Image Process. 27(9): 4623-4637 (2018) - [j65]Donghwa Shin
Thermal Management of Batteries Using Supercapacitor Hybrid Architecture With Idle Period Insertion Strategy. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1159-1170 (2018) - [c198]Sara Vinco, Lorenzo Bottaccioli
GIS-based optimal photovoltaic panel floorplanning for residential installations. DATE 2018: 437-442 - [c197]Daniele Jahier Pagliari
All-digital embedded meters for on-line power estimation. DATE 2018: 737-742 - [c196]Yukai Chen
Battery-aware Design Exploration of Scheduling Policies for Multi-sensor Devices. ACM Great Lakes Symposium on VLSI 2018: 201-206 - [c195]Sara Vinco, Enrico Macii, Massimo Poncino:
Optimal Topology-Aware PV Panel Floorplanning with Hybrid Orientation. ACM Great Lakes Symposium on VLSI 2018: 491-494 - [c194]Alberto Bocca, Yukai Chen
Fundamental Feature Extraction of the Battery Charge Phase from Product Data. ISCAS 2018: 1-4 - [c193]Daniele Jahier Pagliari
Application-Driven Synthesis of Energy-Efficient Reconfigurable-Precision Operators. ISCAS 2018: 1-5 - [c192]Sara Vinco, Lorenzo Bottaccioli, Edoardo Patti, Andrea Acquaviva, Massimo Poncino:
A Compact PV Panel Model for Cyber-Physical Systems in Smart Cities. ISCAS 2018: 1-5 - [c191]Daniele Jahier Pagliari
Dynamic Bit-width Reconfiguration for Energy-Efficient Deep Learning Hardware. ISLPED 2018: 47:1-47:6 - [c190]Donkyu Baek, Yukai Chen
Battery-Aware Energy Model of Drone Delivery Tasks. ISLPED 2018: 49:1-49:6 - [c189]Daniele Apiletti, Claudia Barberis, Tania Cerquitelli, Alberto Macii
iSTEP, an Integrated Self-Tuning Engine for Predictive Maintenance in Industry 4.0. ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018: 924-931 - 2017
- [j64]Alberto Bocca, Alberto Macii
A Modular Framework for Battery Modeling in Electronic Designs. J. Low Power Electron. 13(3): 371-381 (2017) - [j63]Kim Grüttner, Ralph Görgen, Sören Schreiner, Fernando Herrera, Pablo Peñil
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties. Microprocess. Microsystems 51: 39-55 (2017) - [j62]Sara Vinco
A Layered Methodology for the Simulation of Extra-Functional Properties in Smart Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(10): 1702-1715 (2017) - [j61]Daniele Jahier Pagliari
Approximate Energy-Efficient Encoding for Serial Interfaces. ACM Trans. Design Autom. Electr. Syst. 22(4): 64:1-64:25 (2017) - [c188]Daniele Jahier Pagliari
A methodology for the design of dynamic accuracy operators by runtime back bias. DATE 2017: 1165-1170 - [c187]Yukai Chen
A circuit-equivalent battery model accounting for the dependency on load frequency. DATE 2017: 1177-1182 - [c186]Yukai Chen
Workload-driven frequency-aware battery sizing. ISLPED 2017: 1-6 - [c185]Daniele Jahier Pagliari
Optimal content-dependent dynamic brightness scaling for OLED displays. PATMOS 2017: 1-6 - 2016
- [j60]Valerio Tenace
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs. IEEE Trans. Circuits Syst. II Express Briefs 63-II(12): 1111-1115 (2016) - [c184]Daniele Jahier Pagliari
Serial T0: approximate bus encoding for energy-efficient transmission of sensor signals. DAC 2016: 14:1-14:6 - [c183]Daniele Jahier Pagliari, Massimo Poncino, Enrico Macii:
Low-overhead adaptive constrast enhancement and power reduction for OLEDs. DATE 2016: 343-348 - [c182]Ralph Görgen, Kim Grüttner, Fernando Herrera, Pablo Peñil
CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties. DSD 2016: 286-293 - [c181]Sara Vinco, Michele Lora
IP-XACT for smart systems design: extensions for the integration of functional and extra-functional models. FDL 2016: 1-8 - [c180]Valerio Tenace
Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture. ACM Great Lakes Symposium on VLSI 2016: 145-150 - [c179]Sara Vinco, Yukai Chen
A Unified Model of Power Sources for the Simulation of Electrical Energy Systems. ACM Great Lakes Symposium on VLSI 2016: 281-286 - [c178]Daniele Jahier Pagliari
Approximate Differential Encoding for Energy-Efficient Serial Communication. ACM Great Lakes Symposium on VLSI 2016: 421-426 - [c177]Yukai Chen
Fast Thermal Simulation using SystemC-AMS. ACM Great Lakes Symposium on VLSI 2016: 427-432 - [c176]Valerio Tenace
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies. ISCAS 2016: 2897 - [c175]Yukai Chen
A Li-Ion Battery Charge Protocol with Optimal Aging-Quality of Service Trade-off. ISLPED 2016: 40-45 - [c174]Yukai Chen
Frequency domain characterization of batteries for the design of energy storage subsystems. VLSI-SoC 2016: 1-6 - [c173]Valerio Tenace
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits. VLSI-SoC 2016: 1-6 - [c172]Valerio Tenace
Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits. VLSI-SoC (Selected Papers) 2016: 60-82 - 2015
- [j59]Sandeep Miryala, Valerio Tenace
Ultra-low power circuits using graphene p-n junctions and adiabatic computing. Microprocess. Microsystems 39(8): 962-972 (2015) - [j58]Nicola Bombieri
Addressing the Smart Systems design challenge: The SMAC platform. Microprocess. Microsystems 39(8): 1158-1173 (2015) - [j57]Donghwa Shin, Massimo Poncino, Enrico Macii, Naehyuck Chang:
A Statistical Model-Based Cell-to-Cell Variability Management of Li-ion Battery Pack. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(2): 252-265 (2015) - [c171]Valerio Tenace
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits. DAC 2015: 128:1-128:6 - [c170]Sandeep Miryala, Valerio Tenace
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. ACM Great Lakes Symposium on VLSI 2015: 39-44 - [c169]Yukai Chen
Characterizing the Activity Factor in NBTI Aging Models for Embedded Cores. ACM Great Lakes Symposium on VLSI 2015: 75-78 - [c168]Roberto Giorgio Rizzo, Sandeep Miryala, Andrea Calimera
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. ACM Great Lakes Symposium on VLSI 2015: 253-258 - [c167]Daniele Jahier Pagliari
An automated design flow for approximate circuits based on reduced precision redundancy. ICCD 2015: 86-93 - [c166]Alberto Bocca, Alessandro Sassone, Alberto Macii
An aging-aware battery charge scheme for mobile devices exploiting plug-in time patterns. ICCD 2015: 407-410 - [c165]Alberto Bocca, Alessandro Sassone, Donghwa Shin, Alberto Macii
An equation-based battery cycle life model for various battery chemistries. VLSI-SoC 2015: 57-62 - [c164]Alberto Bocca, Alessandro Sassone, Donghwa Shin, Alberto Macii
A Temperature-Aware Battery Cycle Life Model for Different Battery Chemistries. VLSI-SoC (Selected Papers) 2015: 109-130 - 2014
- [j56]Sandeep Miryala, Matheus Oleiro, Letícia Maria Bolzani Pöhls, Andrea Calimera
Modeling of Physical Defects in PN Junction Based Graphene Devices. J. Electron. Test. 30(3): 357-370 (2014) - [j55]Valerio Tenace
Row-based body-bias assignment for dynamic thermal clock-skew compensation. Microelectron. J. 45(5): 530-538 (2014) - [j54]Andrea Calimera
Dynamic Indexing: Leakage-Aging Co-Optimization for Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 251-264 (2014) - [j53]Haroon Mahmood
Energy/Lifetime Cooptimization by Cache Partitioning With Graceful Performance Degradation. IEEE Trans. Very Large Scale Integr. Syst. 22(8): 1705-1715 (2014) - [c163]Donghwa Shin, Enrico Macii, Massimo Poncino:
Statistical Battery Models and Variation-Aware Battery Management. DAC 2014: 135:1-135:6 - [c162]Valerio Guarnieri, Massimo Petricca, Alessandro Sassone, Sara Vinco, Nicola Bombieri, Franco Fummi, Enrico Macii, Massimo Poncino:
A cross-level verification methodology for digital IPs augmented with embedded timing monitors. DATE 2014: 1-6 - [c161]Haroon Mahmood, Massimo Poncino, Enrico Macii:
Cache aging reduction with improved performance using dynamically re-sizable cache. DATE 2014: 1-6 - [c160]Donghwa Shin, Massimo Poncino, Enrico Macii:
Thermal management of batteries using a hybrid supercapacitor architecture. DATE 2014: 1-6 - [c159]Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Pass-XNOR logic: A new logic style for P-N junction based graphene circuits. DATE 2014: 1-4 - [c158]Sandeep Miryala, Andrea Calimera
Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates. DSD 2014: 365-371 - [c157]Alessandro Sassone, Donghwa Shin, Alberto Bocca, Alberto Macii
Modeling of the charging behavior of li-ion batteries based on manufacturer's data. ACM Great Lakes Symposium on VLSI 2014: 39-44 - [c156]Massimo Petricca, Donghwa Shin, Alberto Bocca, Alberto Macii
Automated generation of battery aging models from datasheets. ICCD 2014: 483-488 - [c155]Renaud Gillon
Multi-domain simulation as a foundation for the engineering of smart systems: Challenges and the SMAC vision. ICECS 2014: 858-861 - [c154]Donghwa Shin, Alessandro Sassone, Alberto Bocca, Alberto Macii
A compact macromodel for the charge phase of a battery with typical charging protocol. ISLPED 2014: 267-270 - [c153]Sara Vinco, Alessandro Sassone, Franco Fummi, Enrico Macii, Massimo Poncino:
An open-source framework for formal specification and simulation of electrical energy systems. ISLPED 2014: 287-290 - [c152]Sara Vinco, Alessandro Sassone, Davide Lasorsa, Enrico Macii, Massimo Poncino:
A framework for efficient evaluation and comparison of EES Models. PATMOS 2014: 1-8 - 2013
- [j52]Alessandro Sassone, Wei Liu, Andrea Calimera
Modeling and characterization of thermally induced skew on clock distribution networks of nanometric ICs. Microelectron. J. 44(11): 970-976 (2013) - [j51]Wei Liu, Andrea Calimera
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 406-418 (2013) - [c151]Andrea Calimera
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints. DAC 2013: 110:1-110:6 - [c150]Sandeep Miryala, Mehrdad Montazeri, Andrea Calimera, Enrico Macii, Massimo Poncino:
A verilog-a model for reconfigurable logic gates based on graphene pn-junctions. DATE 2013: 877-880 - [c149]Nicola Bombieri
SMAC: Smart Systems Co-design. DSD 2013: 253-259 - [c148]Sandeep Miryala, Andrea Calimera
Delay model for reconfigurable logic gates based on graphene PN-junctions. ACM Great Lakes Symposium on VLSI 2013: 227-232 - [c147]Younghyun Kim
Computer-aided design of electrical energy systems. ICCAD 2013: 194-201 - [c146]Sandeep Miryala, Andrea Calimera
Exploration of different implementation styles for graphene-based reconfigurable gates. ICICDT 2013: 21-24 - [c145]Donghwa Shin, Massimo Poncino, Enrico Macii, Naehyuck Chang:
A statistical model of cell-to-cell variation in Li-ion batteries for system-level design. ISLPED 2013: 94-99 - [c144]Massimo Petricca, Donghwa Shin, Alberto Bocca, Alberto Macii
An automated framework for generating variable-accuracy battery models from datasheet information. ISLPED 2013: 365-370 - [c143]Sandeep Miryala, Andrea Calimera
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices. LATW 2013: 1-6 - [c142]Sandeep Miryala, Andrea Calimera
Power modeling and characterization of Graphene-based logic gates. PATMOS 2013: 223-226 - [c141]Alessandro Sassone, Massimo Petricca, Massimo Poncino, Enrico Macii:
A fully standard-cell delay measurement circuit for timing variability detection. PATMOS 2013: 239-242 - [c140]Massimo Petricca, Donghwa Shin, Alberto Bocca, Alberto Macii
A framework with temperature-aware accuracy levels for battery modeling from datasheets. PATMOS 2013: 265-268 - 2012
- [j50]Hossein Karimiyan Alidash, Andrea Calimera
On-chip process variation-tracking through an all-digital monitoring architecture. IET Circuits Devices Syst. 6(5): 366-373 (2012) - [j49]Andrea Calimera
Design Techniques for NBTI-Tolerant Power-Gating Architectures. IEEE Trans. Circuits Syst. II Express Briefs 59-II(4): 249-253 (2012) - [j48]Andrea Calimera
Design Techniques and Architectures for Low-Leakage SRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(9): 1992-2007 (2012) - [c139]Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino:
IR-drop analysis of graphene-based power distribution networks. DATE 2012: 81-86 - [c138]Alessandro Sassone, Andrea Calimera, Alberto Macii
Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks. DATE 2012: 165-166 - [c137]Yanzhi Wang, Qing Xie, Massoud Pedram, Younghyun Kim
Multiple-source and multiple-destination charge migration in hybrid electrical energy storage systems. DATE 2012: 169-174 - [c136]Haroon Mahmood
Application-specific memory partitioning for joint energy and lifetime optimization. DATE 2012: 364-369 - [c135]Wei Liu, Sandeep Miryala, Valerio Tenace
NBTI effects on tree-like clock distribution networks. ACM Great Lakes Symposium on VLSI 2012: 279-282 - [c134]Mirko Loghi, Haroon Mahmood
Energy-optimal caches with guaranteed lifetime. ISLPED 2012: 141-146 - [c133]Hossein Karimiyan Alidash, Andrea Calimera
On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture. PATMOS 2012: 155-165 - [c132]Haroon Mahmood
Aging-aware caches with graceful degradation of performance. VLSI-SoC 2012: 237-242 - [e2]Naresh R. Shanbhag, Massimo Poncino, Pai H. Chou, Ajith Amerasekera:
International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, USA - July 30 - August 01, 2012. ACM 2012, ISBN 978-1-4503-1249-3 [contents] - 2011
- [j47]Leandro Max de Lima Silva, Andrea Calimera
Power Efficient Variability Compensation Through Clustered Tunable Power-Gating. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 242-253 (2011) - [j46]Ashoka Visweswara Sathanur, Luca Benini
Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating. IEEE Trans. Very Large Scale Integr. Syst. 19(1): 146-151 (2011) - [j45]Ashoka Visweswara Sathanur, Luca Benini
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 469-482 (2011) - [c131]Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino:
Partitioned cache architectures for reduced NBTI-induced aging. DATE 2011: 938-943 - [c130]Andrea Acquaviva, Massimo Poncino, Marco Otella, Michele Sciolla:
System level techniques to improve reliability in high power microcontrollers for automotive applications. DATE 2011: 1123-1124 - [c129]Salvatore Rinaudo, Giuliana Gangemi, Andrea Calimera, Alberto Macii, Massimo Poncino:
Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems. DATE 2011: 1127-1128 - [c128]Andrea Calimera
Buffering of frequent accesses for reduced cache aging. ACM Great Lakes Symposium on VLSI 2011: 295-300 - [c127]Younghyun Kim
Balanced reconfiguration of storage banks in a hybrid electrical energy storage system. ICCAD 2011: 624-631 - [c126]Hossein Karimiyan, Andrea Calimera
An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs. PATMOS 2011: 162-172 - [c125]Karthikeyan Lingasubramanian, Andrea Calimera
Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating. PATMOS 2011: 214-225 - [e1]Naehyuck Chang, Hiroshi Nakamura, Koji Inoue, Kenichi Osada, Massimo Poncino:
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011, Fukuoka, Japan, August 1-3, 2011. IEEE/ACM 2011, ISBN 978-1-61284-660-6 [contents] - 2010
- [j44]Luca Benini
A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits. J. Low Power Electron. 6(1): 44-55 (2010) - [j43]Andrea Calimera
Dual-Vt assignment policies in ITD-aware synthesis. Microelectron. J. 41(9): 547-553 (2010) - [j42]Mirko Loghi, Olga Golubeva
Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Subbanking. IEEE Trans. Computers 59(7): 891-904 (2010) - [j41]Ashutosh Chakraborty, Karthik Duraisami, Prassanna Sithambaram, Alberto Macii
Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(10): 2741-2752 (2010) - [j40]Andrea Calimera
NBTI-Aware Clustered Power Gating. ACM Trans. Design Autom. Electr. Syst. 16(1): 3:1-3:25 (2010) - [j39]Andrea Calimera
Temperature-Insensitive Dual- Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence. IEEE Trans. Very Large Scale Integr. Syst. 18(11): 1608-1620 (2010) - [c124]Wei Liu, Alberto Nannarelli, Andrea Calimera, Enrico Macii, Massimo Poncino:
Post-placement temperature reduction techniques. DATE 2010: 634-637 - [c123]Andrea Calimera
Aging effects of leakage optimizations for caches. ACM Great Lakes Symposium on VLSI 2010: 95-98 - [c122]David Cuesta, José Luis Ayala, José Ignacio Hidalgo
Thermal-aware floorplanning exploration for 3D multi-core architectures. ACM Great Lakes Symposium on VLSI 2010: 99-102 - [c121]Andrea Acquaviva, Andrea Calimera
An integrated thermal estimation framework for industrial embedded platforms. ACM Great Lakes Symposium on VLSI 2010: 293-298 - [c120]Andrea Calimera
Analysis of NBTI-induced SNM degradation in power-gated SRAM cells. ISCAS 2010: 785-788 - [c119]Andrea Calimera
Dynamic indexing: concurrent leakage and aging optimization for caches. ISLPED 2010: 343-348
2000 – 2009
- 2009
- [j38]Ashoka Visweswara Sathanur, Luca Benini
Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating. J. Low Power Electron. 5(1): 113-121 (2009) - [j37]Andrea Calimera
Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 1979-1993 (2009) - [j36]Franco Fummi, Mirko Loghi, Massimo Poncino, Graziano Pravadelli
A cosimulation methodology for HW/SW validation and performance estimation. ACM Trans. Design Autom. Electr. Syst. 14(2): 23:1-23:32 (2009) - [j35]Mirko Loghi, Paolo Azzoni, Massimo Poncino:
Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching. IEEE Trans. Very Large Scale Integr. Syst. 17(5): 728-732 (2009) - [c118]Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Enabling concurrent clock and power gating in an industrial design flow. DATE 2009: 334-339 - [c117]Cesare Ferri, R. Iris Bahar
Energy-optimal synchronization primitives for single-chip multi-processors. ACM Great Lakes Symposium on VLSI 2009: 141-144 - [c116]Karthik Duraisami, Enrico Macii, Massimo Poncino:
Using soft-edge flip-flops to compensate NBTI-induced delay degradation. ACM Great Lakes Symposium on VLSI 2009: 169-172 - [c115]Andrea Calimera
NBTI-aware sleep transistor design for reliable power-gating. ACM Great Lakes Symposium on VLSI 2009: 333-338 - [c114]Letícia Maria Veiras Bolzani, Andrea Calimera
Placement-aware Clustering for Integrated Clock and Power Gating. ISCAS 2009: 1723-1726 - [c113]Andrea Calimera
NBTI-aware power gating for concurrent leakage and aging optimization. ISLPED 2009: 127-132 - [c112]Wei Liu, Andrea Calimera
On-chip Thermal Modeling Based on SPICE Simulation. PATMOS 2009: 66-75 - [c111]Alberto Bonanno, Alberto Bocca, Alberto Macii
Data-Driven Clock Gating for Digital Filters. PATMOS 2009: 96-105 - [c110]Gaurang Upasani, Andrea Calimera
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering. PATMOS 2009: 227-236 - 2008
- [j34]Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations. Integr. 41(1): 2-8 (2008) - [j33]Andrea Calimera
Thermal-Aware Design Techniques for Nanometer CMOS Circuits. J. Low Power Electron. 4(3): 374-384 (2008) - [j32]Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini
Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 639-649 (2008) - [c109]Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini
A Scalable Algorithmic Framework for Row-Based Power-Gating. DATE 2008: 379-384 - [c108]Enrico Macii, Letícia Maria Veiras Bolzani, Andrea Calimera
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. DSD 2008: 298-303 - [c107]Andrea Calimera
Temperature-insensitive synthesis using multi-vt libraries. ACM Great Lakes Symposium on VLSI 2008: 5-10 - [c106]Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini
Optimal sleep transistor synthesis under timing and area constraints. ACM Great Lakes Symposium on VLSI 2008: 177-182 - [c105]Karthik Duraisami, Enrico Macii, Massimo Poncino:
Energy efficiency bounds of pulse-encoded buses. ACM Great Lakes Symposium on VLSI 2008: 183-188 - [c104]Ashoka Visweswara Sathanur, Andrea Calimera
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. ISCAS 2008: 2761-2764 - [c103]Ashoka Visweswara Sathanur, Luca Benini
Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction. ISLPED 2008: 51-56 - [c102]Andrea Calimera
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. ISLPED 2008: 217-220 - [c101]Ashoka Visweswara Sathanur, Luca Benini
Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating. PATMOS 2008: 42-51 - 2007
- [j31]Franco Fummi, Mirko Loghi, Giovanni Perbellini, Massimo Poncino:
SystemC co-simulation for core-based embedded systems. Des. Autom. Embed. Syst. 11(2-3): 141-166 (2007) - [j30]Francesco Poletti, Antonio Poggiali, Davide Bertozzi, Luca Benini
Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support. IEEE Trans. Computers 56(5): 606-621 (2007) - [j29]Mirko Loghi, Luca Benini
Power macromodeling of MPSoC message passing primitives. ACM Trans. Embed. Comput. Syst. 6(4): 31 (2007) - [c100]Ashoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. DATE 2007: 1544-1549 - [c99]Olga Golubeva, Mirko Loghi, Massimo Poncino, Enrico Macii:
Architectural leakage-aware management of partitioned scratchpad memories. DATE 2007: 1665-1670 - [c98]Olga Golubeva
On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessors. ACM Great Lakes Symposium on VLSI 2007: 489-492 - [c97]Andrea Calimera
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. ACM Great Lakes Symposium on VLSI 2007: 501-504 - [c96]Karthik Duraisami, Prassanna Sithambaram, Ashoka Visweswara Sathanur, Alberto Macii
Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew. ISCAS 2007: 1061-1064 - [c95]Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini
Timing-driven row-based power gating. ISLPED 2007: 104-109 - [c94]Olga Golubeva
Locality-driven architectural cache sub-banking for leakage energy reduction. ISLPED 2007: 274-279 - 2006
- [j28]Kimish Patel, Enrico Macii, Massimo Poncino, Luca Benini:
Energy-Efficient Value Based Selective Refresh for Embedded DRAMS. J. Low Power Electron. 2(1): 70-79 (2006) - [j27]Kimish Patel, Luca Benini
Reducing Conflict Misses by Application-Specific Reconfigurable Indexing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2626-2637 (2006) - [j26]Massimo Poncino, Enrico Macii:
Low-energy RGB color approximation for digital LCD interfaces. IEEE Trans. Consumer Electron. 52(3): 1004-1012 (2006) - [j25]Mirko Loghi, Massimo Poncino, Luca Benini
Cache coherence tradeoffs in shared-memory MPSoCs. ACM Trans. Embed. Comput. Syst. 5(2): 383-407 (2006) - [c93]Ashutosh Chakraborty, Prassanna Sithambaram, Karthik Duraisami, Alberto Macii
Thermal resilient bounded-skew clock tree optimization methodology. DATE 2006: 832-837 - [c92]Franco Fummi, Giovanni Perbellini, Mirko Loghi, Massimo Poncino:
ISS-centric modular HW/SW co-simulation. ACM Great Lakes Symposium on VLSI 2006: 31-36 - [c91]Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino:
STV-Cache: a leakage energy-efficient architecture for data caches. ACM Great Lakes Symposium on VLSI 2006: 404-409 - [c90]Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii
Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits. ISCAS 2006 - [c89]A. Nurrachmat, Enrico Macii, Massimo Poncino:
Low-energy pixel approximation for DVI-based LCD interfaces. ISCAS 2006 - [c88]Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini
Dynamic thermal clock skew compensation using tunable delay buffers. ISLPED 2006: 162-167 - [c87]Mirko Loghi, Massimo Poncino, Luca Benini
Synchronization-driven dynamic speed scaling for MPSoCs. ISLPED 2006: 346-349 - [c86]Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. PATMOS 2006: 214-224 - 2005
- [j24]Sabino Salerno, Enrico Macii, Massimo Poncino:
Energy-efficient bus encoding for LCD digital display interfaces. IEEE Trans. Consumer Electron. 51(2): 624-634 (2005) - [c85]Mirko Loghi, Massimo Poncino:
Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions. DATE 2005: 508-513 - [c84]Mirko Loghi, Paolo Azzoni, Massimo Poncino:
Tag Overflow Buffering: An Energy-Efficient Cache Architecture. DATE 2005: 520-525 - [c83]Franco Fummi, Mirko Loghi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino:
Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation. DATE 2005: 798-803 - [c82]Kimish Patel, Enrico Macii, Massimo Poncino:
Zero clustering: an approach to extend zero compression to instruction caches. ACM Great Lakes Symposium on VLSI 2005: 56-59 - [c81]Mirko Loghi, Martin Letis, Luca Benini, Massimo Poncino:
Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors. ACM Great Lakes Symposium on VLSI 2005: 276-281 - [c80]Andi Nourrachmat, Sabino Salerno, Enrico Macii, Massimo Poncino:
Energy-Efficient Color Approximation for Digital LCD Interfaces. ICCD 2005: 81-86 - [c79]Kimish Patel, Enrico Macii, Massimo Poncino:
Frame Buffer Energy Optimization by Pixel Prediction. ICCD 2005: 98-101 - [c78]Ashutosh Chakraborty, Enrico Macii, Massimo Poncino:
Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding. PATMOS 2005: 297-307 - [c77]Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino:
Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs. PATMOS 2005: 466-476 - 2004
- [c76]Franco Fummi, Stefano Martini, Giovanni Perbellini, Massimo Poncino, Fabio Ricciato, Maura Turolla:
Heterogeneous Co-Simulation of Networked Embedded Systems. DATE 2004: 168-173 - [c75]Franco Fummi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino:
Modeling and Analysis of Heterogeneous Industrial Networks Architectures. DATE 2004: 342-344 - [c74]Franco Fummi, Stefano Martini, Giovanni Perbellini, Massimo Poncino:
Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC. DATE 2004: 564-569 - [c73]Kimish Patel, Enrico Macii, Massimo Poncino:
Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC. DATE 2004: 700-701 - [c72]Alberto Bocca, Sabino Salerno, Enrico Macii, Massimo Poncino:
Energy-efficient bus encoding for LCD displays. ACM Great Lakes Symposium on VLSI 2004: 240-243 - [c71]Mirko Loghi, Massimo Poncino, Luca Benini:
Cycle-accurate power analysis for multiprocessor systems-on-a-chip. ACM Great Lakes Symposium on VLSI 2004: 410-406 - [c70]Kimish Patel, Enrico Macii, Luca Benini
Reducing cache misses by application-specific re-configurable indexing. ICCAD 2004: 125-130 - [c69]Massimo Poncino, Jianwen Zhu:
DynamoSim: a trace-based dynamically compiled instruction set simulator. ICCAD 2004: 131-136 - [c68]Mirko Loghi, Luca Benini, Massimo Poncino:
Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor. ICCD 2004: 393-396 - [c67]Franco Fummi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino:
Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures. ICCD 2004: 496-501 - [c66]Kimish Patel, Enrico Macii, Massimo Poncino:
Energy-performance tradeoffs for the shared memory in multi-processor systems-on-chip. ISCAS (2) 2004: 361-364 - [c65]Sabino Salerno, Enrico Macii, Massimo Poncino:
Crosstalk energy reduction by temporal shielding. ISCAS (2) 2004: 749-752 - [c64]Sabino Salerno, Alberto Bocca, Enrico Macii, Massimo Poncino:
Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces. ISLPED 2004: 206-211 - [c63]Sabino Salerno, Enrico Macii, Massimo Poncino:
A Low-Power Encoding Scheme for GigaByte Video Interfaces. PATMOS 2004: 58-68 - [p1]Kimish Patel, Alberto Macii, Massimo Poncino:
Energy-Efficient Shared Memory Architectures for Multi-Processor Systems-On-Chip. Ultra Low-Power Electronics and Design 2004: 84-102 - 2003
- [j23]Luca Benini, Davide Bertozzi, Davide Bruni, Nicola Drago, Franco Fummi, Massimo Poncino:
SystemC Cosimulation and Emulation of Multiprocessor SoC Designs. Computer 36(4): 53-59 (2003) - [j22]Luca Benini, Davide Bruni, Alberto Macii
Discharge Current Steering for Battery Lifetime Optimization. IEEE Trans. Computers 52(8): 985-995 (2003) - [j21]Luca Benini, Alberto Macii
Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques. ACM Trans. Embed. Comput. Syst. 2(1): 5-32 (2003) - [j20]Luca Benini, Alberto Macii
Scheduling battery usage in mobile systems. IEEE Trans. Very Large Scale Integr. Syst. 11(6): 1136-1143 (2003) - [c62]Luca Benini, Alberto Macii
Energy-aware design techniques for differential power analysis protection. DAC 2003: 36-41 - [c61]Franco Fummi, Giovanni Perbellini, Paolo Gallo, Massimo Poncino, Stefano Martini, Fabio Ricciato:
A timing-accurate modeling and simulation environment for networked embedded systems. DAC 2003: 42-47 - [c60]Alberto Macii, Enrico Macii, Massimo Poncino:
Improving the Efficiency of Memory Partitioning by Address Clustering. DATE 2003: 10018-10023 - [c59]Nicola Drago, Franco Fummi, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino:
Estimation of Bus Performance for a Tuplespace in an Embedded Architecture. DATE 2003: 20188-20195 - [c58]Luca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Massimo Poncino, Fabrizio Pro:
A novel architecture for power maskable arithmetic units. ACM Great Lakes Symposium on VLSI 2003: 136-140 - [c57]Enrico Macii, Massimo Poncino, Sabino Salerno:
Combining wire swapping and spacing for low-power deep-submicron buses. ACM Great Lakes Symposium on VLSI 2003: 198-202 - [c56]Alberto Macii
Increasing the locality of memory access patterns by low-overhead hardware address relocation. ISCAS (5) 2003: 385-388 - [c55]Luca Benini, Angelo Galati, Alberto Macii, Enrico Macii, Massimo Poncino:
Energy-efficient data scrambling on memory-processor interfaces. ISLPED 2003: 26-29 - [c54]Alessandro Fin, Franco Fummi, Massimo Poncino, Graziano Pravadelli
A SystemC-based Framework for Properties Incompleteness Evaluation. MTV 2003: 89-94 - [c53]Maurizio Bruno, Alberto Macii
A Statistic Power Model for Non-synthetic RTL Operators. PATMOS 2003: 208-218 - 2002
- [b1]Alberto Macii, Luca Benini, Massimo Poncino:
Memory design techniques for low energy embedded systems. Kluwer 2002, ISBN 978-0-7923-7690-3, pp. I-VII, 1-144 - [j19]Luca Benini, Luca Macchiarulo
Layout-driven memory synthesis for embedded systems-on-chip. IEEE Trans. Very Large Scale Integr. Syst. 10(2): 96-105 (2002) - [j18]Luca Benini, Alberto Macii
Minimizing memory access energy in embedded systems by selective instruction compression. IEEE Trans. Very Large Scale Integr. Syst. 10(5): 521-531 (2002) - [c52]Luca Macchiarulo
Wire Placement for Crosstalk Energy Minimization in Address Buses. DATE 2002: 158-162 - [c51]Monica Donno, Luca Macchiarulo
Enhanced clustered voltage scaling for low power. ACM Great Lakes Symposium on VLSI 2002: 18-23 - [c50]Luca Benini, Davide Bertozzi, Davide Bruni, Nicola Drago, Franco Fummi, Massimo Poncino:
Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip. ICCD 2002: 494-499 - [c49]Luca Benini, Alberto Macii
Discharge current steering for battery lifetime optimization. ISLPED 2002: 118-123 - 2001
- [j17]Luca Benini, Giovanni De Micheli, Antonio Lioy
Synthesis of power-managed sequential components based oncomputational kernel extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9): 1118-1131 (2001) - [j16]Alberto Macii
Stream synthesis for efficient power simulation based on spectral transforms. IEEE Trans. Very Large Scale Integr. Syst. 9(3): 417-426 (2001) - [j15]Luca Benini, Giuliano Castelli, Alberto Macii
Discrete-time battery models for system-level low-power design. IEEE Trans. Very Large Scale Integr. Syst. 9(5): 630-640 (2001) - [j14]Alessandro Bogliolo
Parameterized RTL power models for soft macros. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 880-887 (2001) - [c48]Luca Benini, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino:
From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip. DAC 2001: 784-789 - [c47]Luca Benini, Giuliano Castelli, Alberto Macii
Extending lifetime of portable systems by battery scheduling. DATE 2001: 197-203 - [c46]Giuliano Castelli, Alberto Macii
Current-controlled policies for battery-driven dynamic power management. ICECS 2001: 959-962 - [c45]Manuela Anton, Ionel Colonescu, Enrico Macii, Massimo Poncino:
Fast characterization of RTL power macromodels. ICECS 2001: 1591-1594 - [c44]Luca Macchiarulo, Enrico Macii, Massimo Poncino:
Low-energy for deep-submicron address buses. ISLPED 2001: 176-181 - 2000
- [j13]Luca Benini, Alberto Macii
Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation. IEEE Des. Test Comput. 17(2): 74-85 (2000) - [j12]Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
A multilevel engine for fast power simulation of realistic inputstreams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(4): 459-472 (2000) - [j11]Fabrizio Ferrandi
Symbolic optimization of interacting controllers based onredundancy identification and removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(7): 760-772 (2000) - [j10]Luca Benini, Alberto Macii
Architectures and synthesis algorithms for power-efficient businterfaces. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 969-980 (2000) - [j9]Luca Benini, Giovanni De Micheli, Alberto Macii
Glitch power minimization by selective gate freezing. IEEE Trans. Very Large Scale Integr. Syst. 8(3): 287-298 (2000) - [c43]Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Synthesis of application-specific memories for power optimization in embedded systems. DAC 2000: 300-303 - [c42]Luca Benini, Giuliano Castelli, Alberto Macii
A Discrete-Time Battery Model for High-Level Power Estimation. DATE 2000: 35-39 - [c41]Luca Benini, Marco Ferrero, Alberto Macii
Supporting system-level power exploration for DSP applications. ACM Great Lakes Symposium on VLSI 2000: 17-22 - [c40]Luca Benini, Alessandro Bogliolo, Enrico Macii, Massimo Poncino, Mihai Surmei:
Regression-based RTL power models for controllers. ACM Great Lakes Symposium on VLSI 2000: 147-152 - [c39]Luca Benini, Alberto Macii, Massimo Poncino:
A recursive algorithm for low-power memory partitioning. ISLPED 2000: 78-83 - [c38]Roberto Zafalon, Massimo Rossello, Enrico Macii, Massimo Poncino:
Power Macromodeling for a High Quality RT-Level Power Estimation. ISQED 2000: 59- - [c37]Alessandro Bogliolo, Enrico Macii, Virgil Mihailovici, Massimo Poncino:
Power Models for Semi-autonomous RTL Macros. PATMOS 2000: 14-23 - [c36]Crina Anton, Pierluigi Civera, Ionel Colonescu, Enrico Macii, Massimo Poncino, Alessandro Bogliolo:
RTL Estimation of Steering Logic Power. PATMOS 2000: 36-46
1990 – 1999
- 1999
- [j8]Luca Benini, Giovanni De Micheli, Antonio Lioy
Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting. IEEE Trans. Computers 48(8): 769-779 (1999) - [j7]Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers. ACM Trans. Design Autom. Electr. Syst. 4(4): 351-375 (1999) - [c35]Luca Benini, Alberto Macii
Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses. DAC 1999: 128-133 - [c34]Luca Benini, Giovanni De Micheli, Enrico Macii, Giuseppe Odasso, Massimo Poncino:
Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms. DAC 1999: 247-252 - [c33]Luca Benini, Giovanni De Micheli, Alberto Macii
Glitch Power Minimization by Gate Freezing. DATE 1999: 163-167 - [c32]Luca Benini, Alberto Macii
Region Compression: A New Scheme for Memory Energy Minimization in Embedded Systems. EUROMICRO 1999: 1311-1317 - [c31]Alberto Macii
Regression-Based Macromodeling for Delay Estimation of Behavioral Components. Great Lakes Symposium on VLSI 1999: 188-191 - [c30]Roberto Corgnati, Enrico Macii, Massimo Poncino:
Clustered Table-Based Macromodels for RTL Power Estimation. Great Lakes Symposium on VLSI 1999: 354-357 - [c29]Alessandro Bogliolo, Roberto Corgnati, Enrico Macii, Massimo Poncino:
Parameterized RTL power models for combinational soft macros. ICCAD 1999: 284-288 - [c28]Luca Benini, Alberto Macii
Selective instruction compression for memory energy reduction in embedded systems. ISLPED 1999: 206-211 - 1998
- [j6]Luca Benini, Enrico Macii, Massimo Poncino, Giovanni De Micheli
Telescopic units: a new paradigm for performance optimization of VLSI designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(3): 220-232 (1998) - [j5]Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer
Power optimization of core-based systems by address bus encoding. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 554-562 (1998) - [c27]Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino:
Computational Kernels and their Application to Sequential Power Optimization. DAC 1998: 764-769 - [c26]Fabrizio Ferrandi
Power Estimation of Behavioral Descriptions. DATE 1998: 762-766 - [c25]Luca Benini, Giovanni De Micheli, Alberto Macii
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding. Great Lakes Symposium on VLSI 1998: 8-12 - [c24]Luca Benini, Giovanni De Micheli, Antonio Lioy
Timed Supersetting and the Synthesis of Telescopic Units. Great Lakes Symposium on VLSI 1998: 331-337 - [c23]Fabrizio Ferrandi
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits. ICCAD 1998: 235-241 - [c22]Alberto Macii
Stream synthesis for efficient power simulation based on spectral transforms. ISLPED 1998: 30-35 - 1997
- [j4]Fabrizio Ferrandi
Testing Core-Based Systems: A Symbolic Methodology. IEEE Des. Test Comput. 14(4): 69-77 (1997) - [c21]Gianpiero Cabodi, Paolo Camurati, Antonio Lioy, Massimo Poncino, Stefano Quer:
A parallel approach to symbolic traversal based on set partitioning. CHARME 1997: 167-184 - [c20]Luca Benini, Enrico Macii, Massimo Poncino:
Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control. DAC 1997: 22-27 - [c19]Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks. ED&TC 1997: 514-520 - [c18]Antonio Lioy, Enrico Macii, Massimo Poncino, Massimo Rossello:
Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering. Great Lakes Symposium on VLSI 1997: 70- - [c17]Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
Fast power estimation for deterministic input streams. ICCAD 1997: 494-501 - [c16]Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer:
System-level power optimization of special purpose applications: the beach solution. ISLPED 1997: 24-29 - 1996
- [j3]Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi:
Automatic state space decomposition for approximate FSM traversal based on circuit analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1451-1464 (1996) - [c15]Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto:
Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques. DAC 1996: 467-470 - [c14]Enrico Macii, Massimo Poncino, Fabrizio Ferrandi
BDD-based testability estimation of VHDL designs. EURO-DAC 1996: 444-449 - [c13]Enrico Macii, Massimo Poncino:
Exact Computation of the Entropy of a Logic Circuit. Great Lakes Symposium on VLSI 1996: 162-167 - [c12]Fabrizio Ferrandi
Test Generation for Networks of Interacting FSMs Using Symbolic Techniques. Great Lakes Symposium on VLSI 1996: 208-213 - [c11]Gianpiero Cabodi, Luciano Lavagno, Enrico Macii, Massimo Poncino, Stefano Quer, Paolo Camurati, Ellen Sentovich:
Enhancing FSM Traversal by Temporary Re-Encoding. ICCD 1996: 6-11 - 1995
- [j2]Enrico Macii, Massimo Poncino:
Using connectivity and spectral methods to characterize the structure of sequential logic circuits. Microprocess. Microprogramming 41(7): 487-500 (1995) - [c10]Srilatha Manne, Abelardo Pardo, R. Iris Bahar
Computing the Maximum Power Cycles of a Sequential Circuit. DAC 1995: 23-28 - [c9]Enrico Macii, Massimo Poncino:
Predicting the functional complexity of combinational circuits by symbolic spectral analysis of Boolean functions. EURO-DAC 1995: 294-299 - [c8]Enrico Macii, Massimo Poncino:
Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks. Great Lakes Symposium on VLSI 1995: 60-65 - [c7]Enrico Macii, Massimo Poncino:
Using symbolic Rademacher-Walsh spectral transforms to evaluate the correlation between Boolean functions. Great Lakes Symposium on VLSI 1995: 112- - 1994
- [c6]Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi:
A State Space Decomposition Algorithm for Approximate FSM Traversal. EDAC-ETC-EUROASIC 1994: 137-141 - [c5]R. Iris Bahar, Gary D. Hachtel, Abelardo Pardo, Massimo Poncino, Fabio Somenzi:
An ADD-based algorithm for shortest path back-tracing of large graphs. Great Lakes Symposium on VLSI 1994: 248-251 - [c4]Gary D. Hachtel, Mariano Hermida de la Rica, Abelardo Pardo, Massimo Poncino, Fabio Somenzi:
Re-encoding sequential circuits to reduce power dissipation. ICCAD 1994: 70-73 - [c3]Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi:
A Structural Approach to State Space Decomposition for Approximate Reachability Analysis. ICCD 1994: 236-239 - 1993
- [j1]Antonio Lioy
A study of the resetability of synchronous sequential circuits. Microprocess. Microprogramming 38(1-5): 395-402 (1993) - [c2]Antonio Lioy, Massimo Poncino:
On the Resetability of Synchronous Sequential Circuits. ISCAS 1993: 1507-1510 - 1991
- [c1]Antonio Lioy
A hierarchical multi-level test generation system. Great Lakes Symposium on VLSI 1991: 54-59
Coauthor Index
[i32] [c237] [i28] [i25] [i22] [j94] [j92] [c231] [c229] [i21] [i19] [i18] [j90] [j88] [c228] [c226] [c224] [c221] [i16] [i15] [i14] [i13] [i12] [i11] [i10] [i6] [i5] [i2] [j82] [c217] [c215] [c214] [c212] [c211] [c207] [c206] [j46] [j45] [j44] [j38] [j37] [j32] [c109] [c106] [c104] [c103] [c101] [j30] [j29] [c100] [c97] [c95] [j28] [j27] [j25] [c91] [c88] [c87] [c81] [c77] [c71] [c70] [c68] [j23] [j22] [j21] [j20] [c62] [c58] [c55] [b1] [j19] [j18] [c50] [c49] [j17] [j15] [c48] [c47] [j13] [j12] [j10] [j9] [c43] [c42] [c41] [c40] [c39] [j8] [j7] [c35] [c34] [c33] [c32] [c28] [j6] [j5] [c27] [c25] [c24] [c20] [c19] [c17] [c16]
Letícia Maria Veiras Bolzani
aka: Letícia Maria Veiras Bolzani Poehls
aka: Letícia Maria Bolzani Pöhls
aka: Letícia Maria Veiras Bolzani Poehls
aka: Letícia Maria Bolzani Pöhls
[i32] [j96] [c237] [c236] [c234] [c233] [c232] [i31] [i30] [i29] [i28] [i27] [i26] [i25] [i24] [i23] [i22] [j94] [j92] [c231] [c229] [i21] [i19] [i18] [i17] [j90] [j88] [j87] [c228] [c226] [c224] [c221] [i16] [i15] [i14] [i13] [i12] [i11] [i10] [i7] [i6] [i5] [i2] [i1] [j82] [c219] [c217] [c215] [c214] [c212] [c211] [c207] [c206]
[j95] [j94] [i20] [j87] [c223] [i8] [i7] [i6] [i1] [j83] [c219] [c213] [c212] [c211] [j77] [c197] [j60] [c180] [c176] [c173] [c172] [j59] [c171] [c170] [c169] [c168] [c167] [j56] [j55] [j54] [c159] [c158] [j52] [j51] [c151] [c150] [c148] [c146] [c143] [c142] [j50] [j49] [j48] [c139] [c138] [c135] [c134] [c133] [j47] [c131] [c129] [c128] [c126] [c125] [j43] [j40] [j39] [c124] [c123] [c121] [c120] [c119] [j37] [c118] [c115] [c114] [c113] [c112] [c110] [j33] [c108] [c107] [c104] [c102] [c100] [c97]
[j80] [j70] [j69] [j68] [c194] [c190] [c189] [j64] [c175] [c166] [c165] [c164] [j55] [c157] [c156] [c154] [j52] [j51] [c144] [c140] [j50] [j48] [c138] [c133] [j47] [j46] [j45] [c129] [c126] [c125] [j44] [j41] [c121] [j38] [j37] [c118] [c114] [c111] [c110] [j34] [j33] [j32] [c109] [c108] [c106] [c104] [c103] [c101] [c100] [c97] [c96] [c95] [c93] [c90] [c88] [c86] [p1] [j22] [j21] [j20] [c62] [c60] [c58] [c56] [c55] [c53] [b1] [j19] [j18] [c51] [c49] [j16] [j15] [c48] [c47] [c46] [j13] [j10] [j9] [c43] [c42] [c41] [c39] [c35] [c33] [c32] [c31] [c28] [c25] [c23] [c22]
[j96] [c237] [c236] [c235] [c234] [c233] [c232] [i31] [i30] [i29] [i28] [i27] [i26] [i25] [i24] [i23] [i22] [j95] [j94] [j92] [j91] [c231] [c230] [c229] [i21] [i20] [i19] [i18] [i17] [j88] [j87] [c228] [c227] [c226] [c224] [c223] [c222] [c221] [i15] [i14] [i13] [i12] [i11] [i10] [i9] [i8] [i7] [i6] [i5] [i3] [i2] [i1] [j84] [j82] [j81] [j80] [j79] [j78] [c219] [c218] [c217] [c215] [c214] [c213] [c212] [c211] [j77] [j76] [c210] [c209] [c208] [c207] [c206] [j75] [j74] [j73] [j72] [j71] [j70] [c205] [c204] [c203] [c202] [c201] [c200] [c199] [j69] [j68] [j67] [j66] [j65] [c198] [c197] [c196] [c195] [c191] [c190] [c189] [j63] [j62] [j61] [c188] [c187] [c186] [c185] [j60] [c184] [c183] [c182] [c181] [c180] [c179] [c178] [c177] [c176] [c175] [c174] [c173] [c172] [j59] [j58] [j57] [c171] [c170] [c169] [c168] [c167] [c166] [c165] [c164] [j56] [j55] [j54] [j53] [c163] [c162] [c161] [c160] [c159] [c158] [c157] [c156] [c154] [c153] [c152] [j52] [j51] [c151] [c150] [c149] [c148] [c146] [c145] [c144] [c143] [c142] [c141] [c140] [j50] [j49] [j48] [c139] [c138] [c136] [c135] [c134] [c133] [c132] [j47] [j46] [j45] [c131] [c128] [c126] [c125] [j44] [j43] [j42] [j41] [j40] [j39] [c124] [c123] [c122] [c121] [c120] [c119] [j38] [j37] [c118] [c116] [c115] [c114] [c113] [c112] [c111] [c110] [j34] [j33] [j32] [c109] [c108] [c107] [c106] [c105] [c104] [c103] [c102] [c101] [c100] [c99] [c97] [c96] [c95] [c94] [j28] [j27] [j26] [c93] [c91] [c90] [c89] [c88] [c86] [j24] [c82] [c80] [c79] [c78] [c77] [c73] [c72] [c70] [c66] [c65] [c64] [c63] [j22] [j20] [c62] [c60] [c58] [c57] [c56] [c55] [j18] [c52] [c51] [c49] [j17] [j16] [j15] [j14] [c48] [c47] [c46] [c45] [c44] [j13] [j12] [j11] [j9] [c43] [c42] [c41] [c40] [c38] [c37] [c36] [j8] [j7] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [j6] [j5] [c27] [c26] [c25] [c24] [c23] [c22] [j4] [c20] [c19] [c18] [c17] [c16] [j3] [c15] [c14] [c13] [c12] [c11] [j2] [c10] [c9] [c8] [c7] [c6] [c3]
[i32] [j96] [c237] [c236] [c235] [c234] [c233] [c232] [i31] [i30] [i29] [i28] [i27] [i26] [i25] [i24] [i23] [i22] [j95] [j94] [j92] [c231] [c230] [c229] [i21] [i20] [i19] [i18] [i17] [j90] [j88] [j87] [c228] [c226] [c224] [c223] [c222] [c221] [c220] [i16] [i15] [i14] [i13] [i12] [i11] [i10] [i9] [i8] [i7] [i6] [i5] [i4] [i2] [i1] [j85] [j83] [j82] [j81] [j80] [j79] [j78] [c219] [c217] [c215] [c214] [c213] [c212] [c211] [j76] [c209] [c207] [c206] [j74] [j73] [j71] [j70] [c205] [c204] [c203] [c202] [c201] [c199] [j66] [c197] [c196] [c193] [c191] [j61] [c188] [c185] [c184] [c183] [c178] [c167]
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