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Yoshinobu Nakagome
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2000 – 2009
- 2004
- [j14]Yoshinobu Nakagome, Bruce Gieseke:
Introduction to the Special Issue. IEEE J. Solid State Circuits 39(4): 547-548 (2004) - 2003
- [j13]Yoshinobu Nakagome, Masashi Horiguchi, Takayuki Kawahara
, Kiyoo Itoh:
Review and future prospects of low-voltage RAM circuits. IBM J. Res. Dev. 47(5-6): 525-552 (2003) - [j12]Shekhar Borkar, Yoshinobu Nakagome:
Guest Editorial. IEEE J. Solid State Circuits 38(5): 687 (2003)
1990 – 1999
- 1999
- [j11]Takashi Sato
A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM. IEEE J. Solid State Circuits 34(5): 653-660 (1999) - 1997
- [j10]Kiyoo Itoh, Yoshinobu Nakagome, Shin'ichiro Kimura, Takao Watanabe:
Limitations and challenges of multigigabit DRAM chip design. IEEE J. Solid State Circuits 32(5): 624-634 (1997) - [j9]Takao Watanabe, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka, Kazushige Ayukawa, Mitsuru Soga, Yuji Tanaka, Yoshimitsu Sugie, Yoshinobu Nakagome:
A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip. IEEE J. Solid State Circuits 32(5): 635-641 (1997) - 1995
- [j8]Norio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome:
A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer. IEEE J. Solid State Circuits 30(3): 251-257 (1995) - [j7]Suguru Tachibana, Hisayuki Higuchi, Koichi Takasugi, Katsuro Sasaki, Toshiaki Yamanaka, Yoshinobu Nakagome:
A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits. IEEE J. Solid State Circuits 30(4): 487-490 (1995) - [j6]Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda:
An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. IEEE J. Solid State Circuits 30(11): 1165-1173 (1995) - [j5]Tomonori Sekiguchi, Masashi Horiguchi, Takeshi Sakata, Yoshinobu Nakagome, Shigeki Ueda, Masakazu Aoki:
Low-noise, high-speed data transmission using a ringing-canceling output buffer. IEEE J. Solid State Circuits 30(12): 1569-1574 (1995) - [j4]Kiyoo Itoh, Katsuro Sasaki, Yoshinobu Nakagome:
Trends in low-power RAM circuit technologies. Proc. IEEE 83(4): 524-543 (1995) - 1994
- [j3]Hitoshi Tanaka, Yoshinobu Nakagome, Jun Etoh, Eiji Yamasaki, Masakazu Aoki, Kazuyuki Miyazawa:
Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs. IEEE J. Solid State Circuits 29(4): 448-453 (1994)
1980 – 1989
- 1989
- [j2]Masakazu Aoki, Shin'ichi Ikenaga, Yoshinobu Nakagome, Masashi Horiguchi, Yasushi Kawase, Yoshifumi Kawamoto, Kiyoo Itoh:
New DRAM noise generation under half-Vcc precharge and its reduction using a transposed amplifier. IEEE J. Solid State Circuits 24(4): 889-894 (1989) - 1988
- [j1]Masashi Horiguchi, Masakazu Aoki, Yoshinobu Nakagome, Shin'ichi Ikenaga, Katsuhiro Shimohigashi:
An experimental large-capacity semiconductor file memory using 16-levels/cell storage. IEEE J. Solid State Circuits 23(1): 27-33 (1988)
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