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Bapi Kar
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2020 – today
- 2020
- [j2]Sumon Kumar Bose
, Bapi Kar
ADEPOS: A Novel Approximate Computing Framework for Anomaly Detection Systems and its Implementation in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(3): 913-926 (2020) - [j1]Bapi Kar
ADIC: Anomaly Detection Integrated Circuit in 65-nm CMOS Utilizing Approximate Computing. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2518-2529 (2020) - [i6]Bapi Kar, Pradeep Kumar Gopalakrishnan, Sumon Kumar Bose, Mohendra Roy, Arindam Basu:
ADIC: Anomaly Detection Integrated Circuit in 65nm CMOS utilizing Approximate Computing. CoRR abs/2008.09442 (2020)
2010 – 2019
- 2019
- [c10]Sumon Kumar Bose, Bapi Kar
ADEPOS: anomaly detection based power saving for predictive maintenance using edge computing. ASP-DAC 2019: 597-602 - [c9]Pradeep Kumar Gopalakrishnan
Live Demonstration: Autoencoder-Based Predictive Maintenance for IoT. ISCAS 2019: 1 - [i5]Sumon Kumar Bose, Bapi Kar, Mohendra Roy, Pradeep Kumar Gopalakrishnan, Lei Zhang, Aakash Patil, Arindam Basu:
ADEPOS: A Novel Approximate Computing Framework for Anomaly Detection Systems and its Implementation in 65nm CMOS. CoRR abs/1912.01853 (2019) - 2018
- [c8]Mohendra Roy
A Stacked Autoencoder Neural Network based Automated Feature Extraction Method for Anomaly detection in On-line Condition Monitoring. SSCI 2018: 1501-1507 - [i4]Mohendra Roy, Sumon Kumar Bose, Bapi Kar, Pradeep Kumar Gopalakrishnan, Arindam Basu:
A Stacked Autoencoder Neural Network based Automated Feature Extraction Method for Anomaly detection in On-line Condition Monitoring. CoRR abs/1810.08609 (2018) - [i3]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction. CoRR abs/1810.10412 (2018) - [i2]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model. CoRR abs/1810.12789 (2018) - [i1]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning. CoRR abs/1811.05161 (2018) - 2016
- [c7]Bapi Kar
An early global routing framework for uniform wire distribution in SoCs. SoCC 2016: 139-144 - [c6]Bapi Kar
A Novel EPE Aware Hybrid Global Route Planner after Floorplanning. VLSID 2016: 595-596 - 2015
- [c5]Bapi Kar
A New Method for Defining Monotone Staircases in VLSI Floorplans. ISVLSI 2015: 107-112 - 2014
- [c4]Sumit Saha, Bapi Kar
A novel architecture for QPSK modulation based on time-mode signal processing. VDAT 2014: 1-6 - [c3]Bapi Kar
Global Routing Using Monotone Staircases with Minimal Bends. VLSID 2014: 369-374 - 2013
- [c2]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
STAIRoute: Global routing using monotone staircase channels. ISVLSI 2013: 90-95 - 2012
- [c1]Bapi Kar, Susmita Sur-Kolay, Sridhar H. Rangarajan, Chittaranjan A. Mandal:
A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts. VDAT 2012: 327-336
Coauthor Index
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