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Plamen Asenov
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2020 – today
- 2024
- [c9]Xi-Wei Lin, Salvatore M. Amoroso, Ko-Hsin Lee, Meng Hsuan Ke, Tue Gunst, Pavel Tikhomirov, Plamen Asenov:
Modeling and Simulation for DRAM and Flash Memory Technology Exploration and Development. IMW 2024: 1-4 - [c8]Leitao Liu, Jingtian Fang, Ashish Pal, Plamen Asenov, Mohit Bajaj, Bei Deng, Xi-Wei Lin, Souvik Mahapatra, Subi Kengeri, El Mehdi Bazizi:
Modeling of Negative Bias Temperature Instability (NBTI) for Gate-All-Around (GAA) Stacked Nanosheet Technology. IRPS 2024: 7 - 2023
- [c7]Victor Moroz, Alexei Svizhenko, Munkang Choi, Plamen Asenov, Jaehyun Lee:
Exploring Power Savings of Gate-All-Around Cryogenic Technology. VLSI Technology and Circuits 2023: 1-2
2010 – 2019
- 2017
- [c6]Asen Asenov, Karim El Sayed, Ricardo Borges, Plamen Asenov, Campbell Millar, Terry Ma:
TCAD based Design-Technology Co-Optimisations in advanced technology nodes. VLSI-DAT 2017: 1-2 - 2016
- [c5]A. Asenov, Yangang Wang, Binjie Cheng, Xingsheng Wang
, Plamen Asenov, Talib Al-Ameri
Nanowire transistor solutions for 5nm and beyond. ISQED 2016: 269-274 - 2015
- [c4]A. Asenov, Jie Ding, Dave Reid, Plamen Asenov, Salvatore M. Amoroso, Fikru Adamu-Lema, Louis Gerrer:
Unified approach for simulation of statistical reliability in nanoscale CMOS transistors from devices to circuits. ISCAS 2015: 2449-2452 - 2013
- [c3]Plamen Asenov, David New, Dave Reid, Campbell Millar, Scott Roy, Asen Asenov:
Evaluating the accuracy of SRAM margin simulation through large scale Monte-Carlo simulations with accurate compact models. ICICDT 2013: 29-32 - 2012
- [c2]Plamen Asenov, Dave Reid, Scott Roy, Campbell Millar, Asen Asenov:
An advanced statistical compact model strategy for SRAM simulation at reduced VDD. ESSDERC 2012: 205-208 - 2011
- [c1]Michael Merrett, Plamen Asenov, Yangang Wang, Mark Zwolinski
Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis. DATE 2011: 1537-1540
Coauthor Index
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