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Dawei Ye
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2020 – today
- 2023
- [j9]Dawei Ye
, Bingxin Cao, Weiping Zhou:
Echo State Network-Enabled Intelligent Smart Sensor Design for Creating a Robotic Nervous System. Int. J. Pattern Recognit. Artif. Intell. 37(7): 2356010:1-2356010:24 (2023) - 2022
- [j8]Rongjin Xu
A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction. Integr. 84: 1-11 (2022) - [j7]Dawei Ye
Erratum to "A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain". IEEE J. Solid State Circuits 57(2): 671 (2022) - [j6]Rongjin Xu
Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2832-2844 (2022) - [c11]Rongjin Xu, Dawei Ye, Sirou Li, Chuanjin Richard Shi:
A 0.021mm2 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency. ISSCC 2022: 214-216 - 2021
- [j5]Dawei Ye
A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain. IEEE J. Solid State Circuits 56(11): 3360-3374 (2021) - [c10]Dawei Ye, Yuting Tu, Wenjun Gong, Rongjin Xu, Chuanjin Richard Shi:
A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference. A-SSCC 2021: 1-3 - [c9]Geng Mu, Dawei Ye
An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording. CICC 2021: 1-2 - 2020
- [j4]Dawei Ye
A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation. IEEE J. Solid State Circuits 55(5): 1386-1400 (2020) - [j3]Liangjian Lyu
A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS. IEEE Trans. Biomed. Circuits Syst. 14(4): 811-824 (2020) - [j2]Liangjian Lyu
A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission. IEEE Trans. Circuits Syst. II Express Briefs 67-II(5): 831-835 (2020) - [c8]Yuting Tu, Rongjin Xu, Dawei Ye
A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [c7]Liangjian Lyu
A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply. ISCAS 2019: 1-4 - [c6]Dawei Ye
A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer. ISCAS 2019: 1-4 - [c5]Dawei Ye
A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity. ISSCC 2019: 414-416 - 2018
- [c4]Yu Wang, Dawei Ye
A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power. ISSCC 2018: 142-144 - 2016
- [j1]Dawei Ye
A 915 MHz 175 µW Receiver Using Transmitted-Reference and Shifted Limiters for 50 dB In-Band Interference Tolerance. IEEE J. Solid State Circuits 51(12): 3114-3124 (2016) - [c3]Dawei Ye
26.2 An Ultra-Low-Power receiver using transmitted-reference and shifted limiters for in-band interference resilience. ISSCC 2016: 438-439 - 2013
- [c2]Dawei Ye
A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing. ISCAS 2013: 169-172 - 2011
- [c1]Ying Wu, Xiaodong Liu, Dawei Ye
A 0.13µm CMOS ΔΣ PLL FM transmitter. NORCHIP 2011: 1-4
Coauthor Index
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