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Jong-Hyeok Yoon
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2020 – today
- 2024
- [c19]Jaehyun Lee, Dong-gu Choi, Minyoung Song
, Gain Kim, Jong-Hyeok Yoon:
BEE-SLAM: A 65nm 17.96 TOPS/W 97.55%-Sparse-Activity Hybrid Mixed-Signal/Digital Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics. CICC 2024: 1-2 - [c18]Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. ISSCC 2024: 482-484 - [c17]Sehwan Lee, Taeryoung Seol, Geunha Kim, Minyoung Song, Gain Kim, Jong-Hyeok Yoon, Arup K. George, Junghyup Lee:
A 97dB-PSRR 178.4dB-FOMDR Calibration-Free VCO-ΔΣ ADC Using a PVT-Insensitive Frequency-Locked Differential Regulation Scheme for Multi-Channel ExG Acquisition. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c16]Seongyeon Yu, Namwook Hur, Wansun Kim, Mann-Ho Cho, Hyunchul Sohn, Joonki Suh, Hongsik Jeong, Jong-Hyeok Yoon:
A PRAM-based PIM Macro Using the Gilbert Multiplier-based Active Feedback and Input-aware SAR ADC. ISOCC 2023: 21-22 - [c15]Geunha Kim, Sehwan Lee, Taeryoung Seol
A 1V-Supply $1.85\mathrm{V}_{\text{PP}}$ -Input-Range 1kHz-BW 181.9dB-FOMDR179.4dB-FOMSNDR 2nd-Order Noise-Shaping SAR-ADC with Enhanced Input Impedance in 0.18μm CMOS. ISSCC 2023: 484-485 - 2022
- [j12]Jong-Hyeok Yoon
A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection. IEEE J. Solid State Circuits 57(1): 68-79 (2022) - [j11]Jong-Hyeok Yoon
A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding. IEEE J. Solid State Circuits 57(3): 845-857 (2022) - [j10]Foroozan Karimzadeh
BitS-Net: Bit-Sparse Deep Neural Network for Energy-Efficient RRAM-Based Compute-In-Memory. IEEE Trans. Circuits Syst. I Regul. Pap. 69(5): 1952-1961 (2022) - [c14]Sangwoo Jung
DualPIM: A Dual-Precision and Low-Power CNN Inference Engine Using SRAM- and eDRAM-based Processing-in-Memory Arrays. AICAS 2022: 70-73 - [c13]Brian Crafton, Zishen Wan, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury:
Improving compute in-memory ECC reliability with successive correction. DAC 2022: 745-750 - [c12]Brian Crafton, Connor Talley
Characterization and Mitigation of IR-Drop in RRAM-based Compute In-Memory. ISCAS 2022: 70-74 - [c11]Jaehyun Lee, Jong-Hyeok Yoon:
A Neuromorphic SLAM Accelerator Supporting Multi-Agent Error Correction in Swarm Robotics. ISOCC 2022: 241-242 - 2021
- [j9]Jong-Hyeok Yoon
NeuroSLAM: A 65-nm 7.25-to-8.79-TOPS/W Mixed-Signal Oscillator-Based SLAM Accelerator for Edge Robotics. IEEE J. Solid State Circuits 56(1): 66-78 (2021) - [c10]Brian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga
CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation. A-SSCC 2021: 1-3 - [c9]Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation. CICC 2021: 1-2 - [c8]Brian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, Arijit Raychowdhury:
Statistical Optimization of Compute In-Memory Performance Under Device Variation. ISLPED 2021: 1-6 - [c7]Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification. ISSCC 2021: 404-406 - 2020
- [j8]Jong-Hyeok Yoon
3.125-to-28.125 Gb/s 4.72 mW/Gb/s Multi- Standard Parallel Transceiver Supporting Channel-Independent Operation in 40-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(8): 2647-2658 (2020) - [j7]Sejun Jeon
A Framed-Pulsewidth Modulation Transceiver for High-Speed Broadband Communication Links. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(8): 2825-2835 (2020) - [c6]Jong-Hyeok Yoon, Arijit Raychowdhury:
31.1 A 65nm 8.79TOPS/W 23.82mW Mixed-Signal Oscillator-Based NeuroSLAM Accelerator for Applications in Edge Robotics. ISSCC 2020: 478-480
2010 – 2019
- 2019
- [j6]Kyeongha Kwon
An Electronic Dispersion Compensation Transceiver for 10- and 28-Gb/s Directly Modulated Lasers-Based Optical Links. IEEE J. Solid State Circuits 54(1): 55-64 (2019) - 2018
- [c5]Jong-Hyeok Yoon, Kyeongha Kwon, Hyeon-Min Bae:
A 3.125-to-28.125 Gb/s multi-standard transceiver with a fully channel-independent operation in 40nm CMOS. CICC 2018: 1-4 - [c4]Kyeongha Kwon, Jong-Hyeok Yoon, Hanho Choi, Younho Jeon, Jaehyeok Yang, Bongjin Kim, Soon-Won Kwon, Minsik Kim, Sejun Jeon, Hyosup Won, Hyeon-Min Bae:
A 28Gb/s transceiver with chirp-managed EDC for DML systems. ISSCC 2018: 264-266 - [c3]Sejun Jeon, Woohyun Kwon
A 20Gb/s transceiver with framed-pulsewidth modulation in 40nm CMOS. ISSCC 2018: 270-272 - 2017
- [j5]Jong-Hyeok Yoon
A DC-to-12.5 Gb/s 9.76 mW/Gb/s All-Rate CDR With a Single LC VCO in 90 nm CMOS. IEEE J. Solid State Circuits 52(3): 856-866 (2017) - 2016
- [j4]Joon-Yeong Lee, Jaehyeok Yang, Jong-Hyeok Yoon, Soon-Won Kwon
A 4×10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2310-2320 (2016) - 2015
- [j3]Hyosup Won, Taehun Yoon, Jinho Han, Joon-Yeong Lee, Jong-Hyeok Yoon, Taeho Kim, Jeong-Sup Lee, Sangeun Lee, Kwangseok Han, Jinhee Lee, Jinho Park, Hyeon-Min Bae:
A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS. IEEE J. Solid State Circuits 50(2): 399-413 (2015) - [j2]Kyeongha Kwon, Jong-Hyeok Yoon, Hyeon-Min Bae:
A 6 Gb/s Transceiver With a Nonlinear Electronic Dispersion Compensator for Directly Modulated Distributed-Feedback Lasers. IEEE J. Solid State Circuits 50(2): 503-514 (2015) - [c2]Jong-Hyeok Yoon, Soon-Won Kwon
A DC-to-12.5Gb/s 4.88mW/Gb/s all-rate CDR with a single LC VCO in 90nm CMOS. CICC 2015: 1-4 - 2014
- [j1]Joon-Yeong Lee, Jong-Hyeok Yoon, Hyeon-Min Bae:
A 10-Gb/s CDR With an Adaptive Optimum Loop-Bandwidth Calibrator for Serial Communication Links. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2466-2472 (2014) - [c1]Kyeongha Kwon, Jong-Hyeok Yoon, Soon-Won Kwon
8.1 A 6Gb/s transceiver with a nonlinear electronic dispersion compensator for directly modulated distributed-feedback lasers. ISSCC 2014: 138-139
Coauthor Index
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