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Dinesh Gaitonde
2020 – today
- 2023
- [c18]Abhishek Kumar Jain, Chirag Ravishankar, Hossein Omidian, Sharan Kumar, Maithilee Kulkarni, Aashish Tripathi, Dinesh Gaitonde:
Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs. FCCM 2023: 133-143 - [c17]Shashwat Shrivastava
, Stefan Nikolic
, Chirag Ravishankar
, Dinesh Gaitonde
, Mirjana Stojilovic
:
Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing. FPGA 2023: 231 - [c16]Dinesh Gaitonde:
AMD Next-Generation FPGA Built from Chiplets. HCS 2023: 1-28 - [c15]Shashwat Shrivastava, Stefan Nikolic
, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic:
IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck. ICCAD 2023: 1-9 - 2022
- [c14]Hossein Omidian, Eddie Hung, Dinesh Gaitonde:
100% Visibility at MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs. ARC 2022: 1-16 - 2021
- [c13]Abhishek Kumar Jain
, Sharan Kumar, Aashish Tripathi, Dinesh Gaitonde:
Sparse Deep Neural Network Acceleration on HBM-Enabled FPGA Platform. HPEC 2021: 1-7 - 2020
- [c12]Abhishek Kumar Jain
, Hossein Omidian, Henri Fraisse, Mansimran Benipal, Lisa Liu, Dinesh Gaitonde:
A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs. FPL 2020: 127-132
2010 – 2019
- 2019
- [c11]Brian Gaide, Dinesh Gaitonde, Chirag Ravishankar, Trevor Bauer:
Xilinx Adaptive Compute Acceleration Platform: VersalTM Architecture. FPGA 2019: 84-93 - [c10]Ian Swarbrick, Dinesh Gaitonde, Sagheer Ahmad
, Brian Gaide, Ygal Arbel:
Network-on-Chip Programmable Platform in VersalTM ACAP Architecture. FPGA 2019: 212-221 - [c9]Ian Swarbrick, Dinesh Gaitonde, Sagheer Ahmad
, Bala Jayadev, Jeff Cuppett, Abbas Morshed, Brian Gaide, Ygal Arbel:
Versal Network-on-Chip (NoC). Hot Interconnects 2019: 13-17 - 2018
- [c8]Henri Fraisse, Dinesh Gaitonde:
A SAT-based Timing Driven Place and Route Flow for Critical Soft IP. FPL 2018: 8-15 - [c7]Chirag Ravishankar, Dinesh Gaitonde, Trevor Bauer:
Placement Strategies for 2.5D FPGA Fabric Architectures. FPL 2018: 16-20 - [c6]Chirag Ravishankar, Henri Fraisse, Dinesh Gaitonde:
SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAs. FPT 2018: 118-125 - 2016
- [c5]Henri Fraisse, Abhishek Joshi, Dinesh Gaitonde, Alireza Kaviani:
Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock Network. FPGA 2016: 74-79 - 2015
- [c4]Shant Chandrakar, Dinesh Gaitonde, Trevor Bauer:
Enhancements in UltraScale CLB Architecture. FPGA 2015: 108-116 - 2014
- [c3]Steve Young, Dinesh Gaitonde:
High capacity and high performance 20nm FPGAs. Hot Chips Symposium 2014: 1-21
1990 – 1999
- 1999
- [c2]Chaitali Chakrabarti, Dinesh Gaitonde:
Instruction level power model of microcontrollers. ISCAS (1) 1999: 76-79 - 1998
- [c1]Binay Ackalloor, Dinesh Gaitonde:
An overview of library characterization in semi-custom design. CICC 1998: 305-312
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last updated on 2025-03-04 21:19 CET by the dblp team
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