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Samira Ataei
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2020 – today
- 2021
- [j2]Samira Ataei
, Wenmian Hua, Yihang Yang, Rajit Manohar
An Open-Source EDA Flow for Asynchronous Logic. IEEE Des. Test 38(2): 27-37 (2021) - 2020
- [c10]Samira Ataei, Rajit Manohar:
Shared-Staticizer for Area-Efficient Asynchronous Circuits. ASYNC 2020: 94-101
2010 – 2019
- 2019
- [c9]Samira Ataei, Rajit Manohar:
AMC: An Asynchronous Memory Compiler. ASYNC 2019: 1-8 - 2018
- [j1]Samira Ataei, James E. Stine
A 64 kB Approximate SRAM Architecture for Low-Power Video Applications. IEEE Embed. Syst. Lett. 10(1): 10-13 (2018) - [c8]Samira Ataei, James E. Stine
A Methodology for Low-Power Approximate Embedded SRAM Within Multimedia Applications. SoCC 2018: 266-271 - 2017
- [c7]Samira Ataei, James E. Stine
A Reconfigurable Replica Bitline to Determine Optimum SRAM Sense Amplifier Set Time. ACM Great Lakes Symposium on VLSI 2017: 269-274 - [c6]Rabin Thapa, Samira Ataei, James E. Stine
WIP. Open-source standard cell characterization process flow on 45 nm (FreePDK45), 0.18 µm, 0.25 µm, 0.35 µm and 0.5 µm. MSE 2017: 5-6 - [c5]Samira Ataei, Matthew Gaalswyk, James E. Stine
A high performance multi-port SRAM for low voltage shared memory systems in 32 nm CMOS. MWSCAS 2017: 1236-1239 - 2016
- [c4]Matthew R. Guthaus
OpenRAM: an open-source memory compiler. ICCAD 2016: 93 - [c3]Samira Ataei, James E. Stine
A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS. ICCD 2016: 499-506 - 2015
- [c2]Samira Ataei, James E. Stine
Multi Replica Bitline Delay Technique for Variation Tolerant Timing of SRAM Sense Amplifiers. ACM Great Lakes Symposium on VLSI 2015: 173-178 - [c1]Samira Ataei, James E. Stine
A differential single-port 8T SRAM bitcell for variability tolerance and low voltage operation. IGSC 2015: 1-6
Coauthor Index
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