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Matthew R. Guthaus
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2020 – today
- 2024
- [j10]Matthew Guthaus
, Kwantae Kim
Open-Source Silicon - Unleashing Innovation and Collaboration. IEEE Des. Test 41(6): 5-7 (2024) - [i4]Bugra Onal, Eren Dogan, Muhammad Hadir Khan, Matthew R. Guthaus:
GAT-Steiner: Rectilinear Steiner Minimal Tree Prediction Using GNNs. CoRR abs/2407.01440 (2024) - [i3]Muhammad Hadir Khan, Bugra Onal, Eren Dogan, Matthew R. Guthaus:
VLSI Hypergraph Partitioning with Deep Learning. CoRR abs/2409.01387 (2024) - 2023
- [c50]Jesse Cirimelli-Low, Muhammad Hadir Khan, Samuel Crow, Amogh Lonkar, Bugra Onal, Andrew D. Zonenberg, Matthew R. Guthaus:
SRAM Design with OpenRAM in SkyWater 130nm. ISCAS 2023: 1-5 - [c49]Farhad Modaresi, Matthew Guthaus, Jason K. Eshraghian
OpenSpike: An OpenRAM SNN Accelerator. ISCAS 2023: 1-5 - [i2]Farhad Modaresi
OpenSpike: An OpenRAM SNN Accelerator. CoRR abs/2302.01015 (2023) - [i1]Matthew Guthaus, Christopher Batten, Erik Brunvand, Pierre-Emmanuel Gaillardon, David M. Harris, Rajit Manohar, Pinaki Mazumder, Larry T. Pileggi, James E. Stine:
NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report. CoRR abs/2311.02055 (2023)
2010 – 2019
- 2019
- [j9]Riadul Islam
HCDN: Hybrid-Mode Clock Distribution Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 251-262 (2019) - [c48]Bin Wu, James E. Stine
Fast and Area-Efficient SRAM Word-Line Optimization. ISCAS 2019: 1-5 - [c47]Hunter Nichols, Michael Grimes, Jennifer Sowash, Jesse Cirimelli-Low, Matthew R. Guthaus
Automated Synthesis of Multi-Port Memories and Control. VLSI-SoC 2019: 59-64 - [c46]Bin Wu, Matthew R. Guthaus
Bottom-Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization. VLSI-SoC 2019: 305-310 - 2018
- [j8]Riadul Islam
DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 2108-2117 (2018) - 2017
- [j7]Riadul Islam
CMCS: Current-Mode Clock Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1054-1062 (2017) - [c45]Rajsaktish Sankaranarayanan, Matthew R. Guthaus:
Energy Savings and Performance Improvement in Subthreshold Using Adaptive Body Bias. ACM Great Lakes Symposium on VLSI 2017: 431-434 - [c44]Elnaz Ebrahimi, Matthew R. Guthaus
Timing speculative SRAM. ISCAS 2017: 1-4 - [c43]Daphne I. Gorman, Matthew R. Guthaus, Jose Renau:
Architectural opportunities for novel dynamic EMI shifting (DEMIS). MICRO 2017: 774-785 - 2016
- [c42]Matthew R. Guthaus
OpenRAM: an open-source memory compiler. ICCAD 2016: 93 - [c41]Samira Ataei, James E. Stine
A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS. ICCD 2016: 499-506 - 2015
- [j6]Riadul Islam, Matthew R. Guthaus:
Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(4): 1156-1164 (2015) - [c40]Hany Ahmed Fahmy, Ping-Yao Lin, Riadul Islam, Matthew R. Guthaus:
Switched capacitor quasi-adiabatic clocks. ISCAS 2015: 1398-1401 - [c39]Benjamin M. LaCara, Ping-Yao Lin, Matthew R. Guthaus:
Multi-frequency resonant clocks. ISCAS 2015: 1402-1405 - [c38]Ping-Yao Lin, Hany Ahmed Fahmy, Riadul Islam, Matthew R. Guthaus:
LC resonant clock resource minimization using compensation capacitance. ISCAS 2015: 1406-1409 - [c37]Riadul Islam, Hany Ahmed Fahmy, Ping-Yao Lin, Matthew R. Guthaus
Differential current-mode clock distribution. MWSCAS 2015: 1-4 - 2014
- [j5]Jeren Samandari-Rad, Matthew R. Guthaus
Confronting the Variability Issues Affecting the Performance of Next-Generation SRAM Design to Optimize and Predict the Speed and Yield. IEEE Access 2: 577-601 (2014) - [c36]Riadul Islam, Matthew R. Guthaus:
Current-mode clock distribution. ISCAS 2014: 1203-1206 - 2013
- [j4]Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis
Revisiting automated physical synthesis of high-performance clock networks. ACM Trans. Design Autom. Electr. Syst. 18(2): 31:1-31:27 (2013) - [c35]Sheldon Logan, Matthew R. Guthaus:
Redundant C4 power pin placement to ensure robust power grid delivery. MWSCAS 2013: 449-452 - [c34]Sheldon Logan, Matthew R. Guthaus:
A decap placement methodology for reducing joule heating and temperature in PSN interconnect. MWSCAS 2013: 840-843 - [c33]Janusz Rajski, Miodrag Potkonjak, Adit D. Singh, Abhijit Chatterjee, Zain Navabi, Matthew R. Guthaus, Sezer Gören:
Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. VLSI-SoC 2013 - [e2]Andreas Burg, Ayse K. Coskun, Matthew R. Guthaus, Srinivas Katkoori, Ricardo Reis:
VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers. IFIP Advances in Information and Communication Technology 418, Springer 2013, ISBN 978-3-642-45072-3 [contents] - 2012
- [j3]Xuchu Hu, Matthew R. Guthaus:
Distributed LC Resonant Clock Grid Synthesis. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(11): 2749-2760 (2012) - [j2]Matthew R. Guthaus, Xuchu Hu, Gustavo Wilke, Guilherme Flach, Ricardo Reis
High-performance clock mesh optimization. ACM Trans. Design Autom. Electr. Syst. 17(3): 33:1-33:17 (2012) - [c32]Xuchu Hu, Walter James Condley, Matthew R. Guthaus
Library-aware resonant clock synthesis (LARCS). DAC 2012: 145-150 - [c31]Curtis Andrus, Matthew R. Guthaus
Lithography-aware layout compaction. ACM Great Lakes Symposium on VLSI 2012: 147-152 - [c30]Matthew R. Guthaus, Baris Taskin:
High-Performance, Low-Power Resonant Clocking: Embedded tutorial. ICCAD 2012: 742-745 - [c29]Jeren Samandari-Rad, Matthew R. Guthaus
VAR-TX: A variability-aware SRAM model for predicting the optimum architecture to achieve minimum access-time for yield enhancement in nano-scaled CMOS. ISQED 2012: 506-515 - [c28]Bennion Redd
Architecture for increased address space in an ultra-low-power microprocessor. MWSCAS 2012: 125-128 - [c27]Matthew R. Guthaus:
Welcome from the general chair. VLSI-SoC 2012 - [c26]Haven Blake Skinner, Xuchu Hu, Matthew R. Guthaus:
Harmonic resonant clocking. VLSI-SoC 2012: 59-64 - [c25]Seokjoong Kim, Matthew R. Guthaus:
SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture. VLSI-SoC (Selected Papers) 2012: 181-195 - [c24]Seokjoong Kim, Matthew R. Guthaus
Dynamic voltage scaling for SEU-tolerance in low-power memories. VLSI-SoC 2012: 207-212 - [c23]Rajsaktish Sankaranarayanan, Matthew R. Guthaus
A single-VDD ultra-low energy sub-threshold FPGA. VLSI-SoC 2012: 219-224 - [e1]Srinivas Katkoori, Matthew R. Guthaus, Ayse K. Coskun, Andreas Burg, Ricardo Reis:
20th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012. IEEE 2012, ISBN 978-1-4673-2657-5 [contents] - 2011
- [c22]Xuchu Hu, Matthew R. Guthaus
Clock tree optimization for Electromagnetic Compatibility (EMC). ASP-DAC 2011: 184-189 - [c21]Seokjoong Kim, Matthew R. Guthaus:
Leakage-aware redundancy for reliable sub-threshold memories. DAC 2011: 435-440 - [c20]Xuchu Hu, Matthew R. Guthaus:
Distributed Resonant clOCK grid Synthesis (ROCKS). DAC 2011: 516-521 - [c19]Walter James Condley, Xuchu Hu, Matthew R. Guthaus
A methodology for local resonant clock synthesis using LC-assisted local clock buffers. ICCAD 2011: 503-506 - [c18]Seokjoong Kim, Matthew R. Guthaus:
Low-power multiple-bit upset tolerant memory optimization. ICCAD 2011: 577-581 - [c17]Matthew R. Guthaus
Distributed LC resonant clock tree synthesis. ISCAS 2011: 1215-1218 - [c16]Sheldon Logan, Matthew R. Guthaus:
Package-chip co-design to increase flip-chip C4 reliability. ISQED 2011: 553-558 - [c15]Walter James Condley, Andrew W. Hill
Advanced logic design through hands-on digital music synthesis. MSE 2011: 17-20 - [c14]Seokjoong Kim, Matthew R. Guthaus:
SNM-aware power reduction and reliability improvement in 45nm SRAMs. VLSI-SoC 2011: 204-207 - 2010
- [c13]Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis
Non-uniform clock mesh optimization with linear programming buffer insertion. DAC 2010: 74-79 - [c12]Derek Chan, Matthew R. Guthaus:
Analysis of power supply induced jitter in actively de-skewed multi-core systems. ISQED 2010: 785-790 - [c11]Walter James Condley, Xuchu Hu, Matthew R. Guthaus:
Analysis of high-performance clock networks with RLC and transmission line effects. SLIP 2010: 51-58
2000 – 2009
- 2009
- [c10]Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau:
Measuring and modeling variabilityusing low-cost FPGAs. FPGA 2009: 286 - [c9]Keven L. Woo, Matthew R. Guthaus:
Fault-tolerant synthesis using non-uniform redundancy. ICCD 2009: 213-218 - [c8]Matthew R. Guthaus:
Teaching VLSI design in 10 weeks. MSE 2009: 41-44 - 2008
- [c7]Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown:
Clock tree synthesis with data-path sensitivity matching. ASP-DAC 2008: 498-503 - 2006
- [b1]Matthew R. Guthaus:
Clock tree analysis and synthesis considering process parameters and variability. University of Michigan, USA, 2006 - [c6]Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown:
Process-induced skew reduction in nominal zero-skew clock trees. ASP-DAC 2006: 84-89 - [c5]Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown:
Clock buffer and wire sizing using sequential programming. DAC 2006: 1041-1046 - 2005
- [j1]Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown:
Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor. IEEE Trans. Computers 54(8): 998-1012 (2005) - [c4]Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown:
Optimization objectives and models of variation for statistical gate sizing. ACM Great Lakes Symposium on VLSI 2005: 313-316 - [c3]Matthew R. Guthaus, Natesan Venkateswaran, Chandu Visweswariah, Vladimir Zolotov:
Gate sizing using incremental parameterized statistical timing analysis. ICCAD 2005: 1029-1036 - 2003
- [c2]Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown:
Increasing the number of effective registers in a low-power processor using a windowed register file. CASES 2003: 125-136 - [c1]Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Matthew R. Guthaus, Richard B. Brown:
A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference. DAC 2003: 520-525
Coauthor Index
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last updated on 2024-12-02 21:30 CET by the dblp team
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