default search action
Jie Gu 0001
Person information
- affiliation: Northwestern University, Department of Electrical and Computer Engineering, Evanston, IL, USA
Other persons with the same name
- Jie Gu — disambiguation page
- Jie Gu 0002
— University of Chinese Academy of Sciences, School of Artificial Intelligence, Beijing, China
- Jie Gu 0003 — Max Linear, Inc., Carlsbad, CA, USA (and 1 more)
- Jie Gu 0004
- Jie Gu 0005
- Jie Gu 0006
- Jie Gu 0007 — Texas Instrumenits, Inc., Dallas, TX, USA
- Jie Gu 0008
- Jie Gu 0009
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
Journal Articles
- 2025
- [j15]Shiyu Guo
Mobile-PBR: A 28-nm Energy-Efficient Rendering Processor for Photorealistic Augmented Reality With Inverse Rendering and Background Clustering. IEEE J. Solid State Circuits 60(1): 125-135 (2025) - [j14]Qiankai Cao
A 65-nm Humanoid Robot System-on-Chip Using Time-Domain 3-D Footstep Planning and Mixed-Signal ZMP Gait Scheduler With Inverse Kinematics. IEEE J. Solid State Circuits 60(4): 1339-1348 (2025) - [j13]Yuhao Ju
A 65 nm General-Purpose Compute-in-Memory Processor Supporting Both General Programming and Deep Learning Tasks. IEEE J. Solid State Circuits 60(4): 1500-1511 (2025) - [j12]Xi Chen
A 65-nm Proactive Power Management Technique With Real-Time Machine Learning Engine for Droop Prediction and Mitigation on Microprocessors. IEEE J. Solid State Circuits 60(6): 2170-2181 (2025) - 2023
- [j11]Yuhao Ju
A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance. IEEE J. Solid State Circuits 58(1): 216-226 (2023) - 2021
- [j10]Tianyu Jia
A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique. IEEE J. Solid State Circuits 56(1): 55-65 (2021) - [j9]Zhengyu Chen
High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification With Pipelined Mixed-Signal Time-Domain Computing. IEEE J. Solid State Circuits 56(2): 624-635 (2021) - [j8]Yijie Wei
A Gesture Classification SoC for Rehabilitation With ADC-Less Mixed-Signal Feature Extraction and Training Capable Neural Network Classifier. IEEE J. Solid State Circuits 56(3): 876-886 (2021) - 2020
- [j7]Tianyu Jia
An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture. IEEE J. Solid State Circuits 55(8): 2259-2269 (2020) - 2019
- [j6]Tianyu Jia
An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor. IEEE J. Solid State Circuits 54(8): 2327-2338 (2019) - [j5]Zhengyu Chen
A Time-Domain Computing Accelerated Image Recognition Processor With Efficient Time Encoding and Non-Linear Logic Operation. IEEE J. Solid State Circuits 54(11): 3226-3237 (2019) - [j4]Zhengyu Chen
R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2655-2667 (2019) - 2018
- [j3]Tianyu Jia
A Fully Integrated Buck Regulator With 2-GHz Resonant Switching for Low-Power Applications. IEEE J. Solid State Circuits 53(9): 2663-2674 (2018) - [j2]Zhengyu Chen
A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 2118-2131 (2018) - [j1]Shuyu Kong
Design and Synthesis of Self-Healing Memristive Circuits for Timing Resilient Processor Design. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2648-2660 (2018)
Conference and Workshop Papers
- 2025
- [c44]Zhiwei Zhong
Headset-Integrated Brain-Machine Interface for Mind Imagery and Control in VR/MR Applications. ASP-DAC 2025: 317-320 - [c43]Qiankai Cao
Humanoid Robot Control: A Mixed-Signal Footstep Planning SoC with ZMP Gait Scheduler and Neural Inverse Kinematics. ASP-DAC 2025: 321-324 - [c42]Qiankai Cao
Modeling, Design and In-situ Demonstration of Bio-inspired Central Pattern Generator and Neuromorphic Computing Circuits for Complex Kinematic Control of Quadruped Robots. ACM Great Lakes Symposium on VLSI 2025: 147-154 - 2024
- [c41]Shiyu Guo
LLM-MARK: A Computing Framework on Efficient Watermarking of Large Language Models for Authentic Use of Generative AI at Local Devices. DAC 2024: 253:1-253:6 - [c40]Yuhao Ju, Ganqi Xu, Jie Gu:
20.4 A 28nm Physics Computing Unit Supporting Emerging Physics-Informed Neural Network and Finite Element Method for Real-Time Scientific Computing on Edge Devices. ISSCC 2024: 366-368 - [c39]Zhiwei Zhong, Yijie Wei, Lance Christopher Go, Jie Gu:
33.2 A Sub-1μJ/class Headset-Integrated Mind Imagery and Control SoC for VR/MR Applications with Teacher-Student CNN and General-Purpose Instruction Set Architecture. ISSCC 2024: 544-546 - [c38]Shiyu Guo, Sachin S. Sapatnekar, Jie Gu:
Software-Hardware Codesign of Ray-Tracing Accelerator for Edge AR/VR With Viewpoint-Focused 3D Construction and Efficient Data Structure. MWSCAS 2024: 267-271 - [c37]Zhiwei Zhong, Yuhao Ju, Jie Gu:
Scalable Physics-Embedded Neural Networks for Real-Time Robotic Control in Embedded Systems. MWSCAS 2024: 823-827 - [c36]Qiankai Cao, Juin Chuen Oh, Jie Gu:
A Mixed-signal 3D Footstep Planning SoC for Motion Control of Humanoid Robots with Embedded Zero-Moment-Point based Gait Scheduler and Neural Inverse Kinematics. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c35]Xi Chen, Aly Shoukry, Tianyu Jia, Xin Zhang
A 65nm Fully-integrated Fast-switching Buck Converter with Resonant Gate Drive and Automatic Tracking. CICC 2023: 1-2 - [c34]Qiankai Cao, Xi Chen, Jie Gu:
Development of Tropical Algebraic Accelerator with Energy Efficient Time-Domain Computing for Combinatorial Optimization and Machine Learning. ISLPED 2023: 1-6 - [c33]Xi Chen, Jiaxiang Feng, Aly Shoukry, Xin Zhang
Proactive Power Regulation with Real-time Prediction and Fast Response Guardband for Fine-grained Dynamic Voltage Droop Mitigation on Digital SoCs. VLSI Technology and Circuits 2023: 1-2 - [c32]Yuhao Ju, Yijie Wei, Xi Chen, Jie Gu:
A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality. VLSI Technology and Circuits 2023: 1-2 - [c31]Yijie Wei, Xi Chen, Jie Gu:
Human Activity Recognition SoC for AR/VR with Integrated Neural Sensing, AI Classifier and Chained Infrared Communication for Multi-chip Collaboration. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c30]Yijie Wei, Xi Chen, Jie Gu:
A 65nm Implantable Gesture Classification SoC for Rehabilitation with Enhanced Data Compression and Encoding for Robust Neural Network Operation Under Wireless Power Condition. CICC 2022: 1-2 - [c29]Yijie Wei, Zhiwei Zhong, Jie Gu:
Human emotion based real-time memory and computation management on resource-limited edge devices. DAC 2022: 487-492 - [c28]Yuhao Ju, Shiyu Guo, Zixuan Liu, Tianyu Jia, Jie Gu:
A Differentiable Neural Computer for Logic Reasoning with Scalable Near-Memory Computing and Sparsity Based Enhancement. ESSCIRC 2022: 93-96 - [c27]Yuhao Ju, Jie Gu:
A 65nm Systolic Neural CPU Processor for Combined Deep Learning and General-Purpose Computing with 95% PE Utilization, High Data Locality and Enhanced End-to-End Performance. ISSCC 2022: 1-3 - [c26]Qiankai Cao, Jie Gu:
A Sparse Convolution Neural Network Accelerator for 3D/4D Point-Cloud Image Recognition on Low Power Mobile Device with Hopping-Index Rule Book for Efficient Coordinate Management. VLSI Technology and Circuits 2022: 106-107 - 2021
- [c25]Zhengyu Chen, Xi Chen, Jie Gu:
15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency. ISSCC 2021: 240-242 - 2020
- [c24]Yijie Wei, Qiankai Cao, Jie Gu, Kofi Otseidu, Levi J. Hargrove:
A Fully-integrated Gesture and Gait Processing SoC for Rehabilitation with ADC-less Mixed-signal Feature Extraction and Deep Neural Network for Classification and Online Training. CICC 2020: 1-4 - [c23]Yijie Wei, Kofi Otseidu, Jie Gu:
Exploration of Design Space and Runtime Optimization for Affective Computing in Machine Learning Empowered Ultra-Low Power SoC. DAC 2020: 1-6 - [c22]Yijie Wei, Qiankai Cao, Levi J. Hargrove, Jie Gu:
A Wearable Bio-signal Processing System with Ultra-low-power SoC and Collaborative Neural Network Classifier for Low Dimensional Data Communication. EMBC 2020: 4002-4007 - [c21]Tianyu Jia, Yuhao Ju, Jie Gu:
31.3 A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators. ISSCC 2020: 482-484 - [c20]Tianyu Jia, Yuhao Ju, Russ Joseph, Jie Gu:
NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End Performance. MICRO 2020: 1097-1109 - [c19]Zhengyu Chen, Sihua Fu, Qiankai Cao, Jie Gu:
A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices. VLSI Circuits 2020: 1-2 - 2019
- [c18]Zhengyu Chen, Hai Zhou, Jie Gu:
Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing. DAC 2019: 67 - [c17]Tianyu Jia, Russ Joseph, Jie Gu:
An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution. ISSCC 2019: 318-320 - [c16]Zhengyu Chen, Jie Gu:
A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput. ISSCC 2019: 324-326 - [c15]Amin Rezaei, Jie Gu, Hi Zhou:
Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries. ISVLSI 2019: 535-540 - 2018
- [c14]Tianyu Jia, Jie Gu:
A Fully-integrated LC-Oscillator Based Buck Regulator with Autonomous Resonant Switching for Low-Power Applications. A-SSCC 2018: 179-182 - [c13]Zhengyu Chen, Jie Gu:
An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation. A-SSCC 2018: 257-260 - [c12]Yuanbo Fan, Tianyu Jia, Jie Gu, Simone Campanoni, Russ Joseph:
Compiler-guided instruction-level clock scheduling for timing speculative processors. DAC 2018: 40:1-40:6 - [c11]Amin Rezaei, Yuanqi Shen, Shuyu Kong, Jie Gu, Hai Zhou:
Cyclic locking and memristor-based obfuscation against CycSAT and inside foundry attacks. DATE 2018: 85-90 - [c10]Tianyu Jia, Russ Joseph, Jie Gu:
An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. ESSCIRC 2018: 94-97 - [c9]Kofi Otseidu, Tianyu Jia, Joshua Bryne, Levi J. Hargrove, Jie Gu:
Design and optimization of edge computing distributed neural processor for biomedical rehabilitation with sensor fusion. ICCAD 2018: 120 - [c8]Zhengyu Chen, Hai Zhou, Jie Gu:
R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing. ICCD 2018: 163-170 - [c7]Josiah D. Hester, Tianyu Jia, Jie Gu:
Holistic Energy Management with μProcessor Co-Optimization in Fully Integrated Battery-Less IoTs. SoCC 2018: 7-12 - 2017
- [c6]Tianyu Jia, Russ Joseph, Jie Gu:
Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management. DAC 2017: 48:1-48:6 - [c5]Shuyu Kong, Jie Gu, Hai Zhou:
Memristor-Based Clock Design and Optimization with In-Situ Tunability. ISVLSI 2017: 427-432 - [c4]Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu:
(Invited) Software-guided greybox design methodology with integrated power and clock management. MWSCAS 2017: 894-897 - 2016
- [c3]Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu:
Exploration of associative power management with instruction governed operation for ultra-low power design. DAC 2016: 152:1-152:6 - [c2]Huanyu Wang, Geng Xie, Jie Gu:
Comprehensive Analysis, Modeling and Design for Hold-Timing Resiliency in Voltage Scalable Design. ISLPED 2016: 22-27 - [c1]Zhengyu Chen, Jie Gu:
Analysis and Design of Energy Efficient Time Domain Signal Processing. ISLPED 2016: 100-105
Informal and Other Publications
- 2021
- [i2]Amin Rezaei, Jie Gu, Hai Zhou:
Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries. IACR Cryptol. ePrint Arch. 2021: 1313 (2021) - 2017
- [i1]Amin Rezaei, Yuanqi Shen, Shuyu Kong, Jie Gu, Hai Zhou:
Cyclic Locking and Memristor-based Obfuscation Against CycSAT and Inside Foundry Attacks. IACR Cryptol. ePrint Arch. 2017: 1176 (2017)
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2025-07-07 21:19 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: