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Francesco Centurelli
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2020 – today
- 2024
- [j38]Riccardo Della Sala
, Francesco Centurelli
Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications. IEEE Access 12: 4642-4659 (2024) - [j37]Riccardo Della Sala
A Novel High Performance Standard-Cell Based ULV OTA Exploiting an Improved Basic Amplifier. IEEE Access 12: 17513-17521 (2024) - [j36]Riccardo Della Sala
On the Feasibility of Cascode and Regulated Cascode Amplifier Stages in ULV Circuits Exploiting MOS Transistors in Deep Subthreshold Operation. IEEE Access 12: 73292-73303 (2024) - [c39]Riccardo Della Sala
Enhancing Performance of Ultra-Low Voltage Body-Driven Comparators Through Clocked Supply Voltage. PRIME 2024: 1-4 - [c38]Riccardo Della Sala
A Novel Technique to Design Ultra-Low Voltage and Ultra-Low Power Inverter-Based OTAs. PRIME 2024: 1-4 - [c37]Valerio Spinogatti, Cristian Bocciarelli, Lorenzo Eusebio, Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti:
A 150 MS/s, 10 bit SAR ADC Featuring a Modified Quasi-Monotonic Switching Scheme. PRIME 2024: 1-5 - 2023
- [j35]Riccardo Della Sala
A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations. IEEE Access 11: 19635-19644 (2023) - [j34]Francesco Centurelli
A Novel Parallel Digitizer With a Pulseless Mixing-Filtering-Processing Architecture and Its Implementation in a SiGe HBT Technology at 40GS/s. IEEE Access 11: 75657-75670 (2023) - [j33]Valerio Spinogatti, Riccardo Della Sala
An Improved Strong Arm Comparator With Integrated Static Preamplifier. IEEE Access 11: 91724-91737 (2023) - [j32]Riccardo Della Sala
A body-driven rail-to-rail 0.3 V operational transconductance amplifier exploiting current gain stages. Int. J. Circuit Theory Appl. 51(5): 1971-1987 (2023) - [j31]Cristian Bocciarelli
A 17 GHz inductorless low-pass filter based on a quasi-Sallen-Key approach. Int. J. Circuit Theory Appl. 51(11): 5066-5084 (2023) - [j30]Alessandro Fava
A Detailed Model of Cyclostationary Noise in Switched-Resistor Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 70(2): 667-679 (2023) - [j29]Cristian Bocciarelli, Francesco Centurelli
High-Accuracy Low-Cost Generalized Complex Pruned Volterra Models for Nonlinear Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 70(9): 3534-3544 (2023) - [c36]Gianluca Barile, Vincenzo Stornelli, Leonardo Pantoli
CMOS Adaptive Biased Second Generation Voltage Conveyor. BATS 2023: 62-67 - [c35]Riccardo Della Sala
A Novel Ultra-Low Voltage Fully Synthesizable Comparator exploiting NAND Gates. PRIME 2023: 21-24 - [c34]Valerio Spinogatti, Cristian Bocciarelli, Francesco Centurelli, Riccardo Della Sala
Robust Body Biasing Techniques for Dynamic Comparators. PRIME 2023: 25-28 - [c33]Cristian Bocciarelli, Francesco Centurelli, Riccardo Della Sala
A 2.5 GHz, 0.6 V Body Driven Dynamic Comparator Exploiting Charge Pump Based Dynamic Biasing. PRIME 2023: 37-40 - [c32]Alessandro Fava, Francesco Centurelli, Andrea Vittimberga, Giuseppe Scotti:
Wide-Band Shared LNA for Large Scale Neural Recording Applications. SMACD 2023: 1-4 - 2022
- [j28]Francesco Centurelli
A Biasing Approach to Design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs. IEEE Access 10: 25892-25900 (2022) - [j27]Riccardo Della Sala
A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs. IEEE Access 10: 98179-98190 (2022) - [j26]Francesco Centurelli
A SiGe HBT 6th-Order 10 GHz Inductor-Less Anti-Aliasing Low-Pass Filter for High-Speed ATI Digitizers. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 100-113 (2022) - [j25]Riccardo Della Sala
Enabling ULV Fully Synthesizable Analog Circuits: The BA Cell, a Standard-Cell-Based Building Block for Analog Design. IEEE Trans. Circuits Syst. II Express Briefs 69(12): 4689-4693 (2022) - [j24]Francesco Centurelli
General Approach to the Calibration of Innovative MFP Multichannel Digitizers. IEEE Trans. Instrum. Meas. 71: 1-14 (2022) - [c31]Riccardo Della Sala
High-efficiency 0.3V OTA in CMOS 130nm technology using current mirrors with gain. PRIME 2022: 69-72 - [c30]Riccardo Della Sala
Sub-μW Front-End Low Noise Amplifier for Neural Recording Applications. PRIME 2022: 305-308 - 2021
- [j23]Francesco Centurelli
A Detailed Model of the Switched-Resistor Technique. IEEE Open J. Circuits Syst. 2: 497-507 (2021) - [j22]Francesco Centurelli
Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 680-691 (2021) - [j21]Giandomenico Amendola, Luigi Boccia
Compact E-Band I/Q Receiver in SiGe BiCMOS for 5G Backhauling Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3098-3102 (2021) - [j20]Francesco Centurelli
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 998-1008 (2021) - [c29]Francesco Centurelli
A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML. ISCAS 2021: 1-5 - 2020
- [j19]Danilo Cellucci, Francesco Centurelli
0.6-V CMOS cascode OTA with complementary gate-driven gain-boosting and forward body bias. Int. J. Circuit Theory Appl. 48(1): 15-27 (2020) - [j18]Francesco Centurelli
Low-power class-AB 4th-order low-pass filter based on current conveyors with dynamic mismatch compensation of biasing errors. Int. J. Circuit Theory Appl. 48(4): 472-484 (2020) - [j17]Francesco Centurelli
An improved reversed miller compensation technique for three-stage CMOS OTAs with double pole-zero cancellation and almost single-pole frequency response. Int. J. Circuit Theory Appl. 48(11): 1990-2005 (2020) - [j16]Francesco Centurelli
Delay models and design guidelines for MCML gates with resistor or PMOS load. Microelectron. J. 99: 104755 (2020)
2010 – 2019
- 2019
- [j15]Francesco Centurelli
High-gain, high-CMRR class AB operational transconductance amplifier based on the flipped voltage follower. Int. J. Circuit Theory Appl. 47(4): 499-512 (2019) - [c28]Francesco Centurelli
A low-power class-AB Gm-C biquad stage in CMOS 40nm technology. ICECS 2019: 294-297 - 2018
- [j14]Francesco Centurelli
A Topology of Fully Differential Class-AB Symmetrical OTA With Improved CMRR. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1504-1508 (2018) - 2017
- [j13]Francesco Centurelli
Fully Differential Class-AB OTA with Improved CMRR. J. Circuits Syst. Comput. 26(11): 1750169:1-1750169:11 (2017) - [c27]Gianluca Barile
Power-efficient dynamic-biased CCII. ECCTD 2017: 1-4 - [c26]Francesco Centurelli
A fully-differential class-AB OTA with CMRR improved by local feedback. ECCTD 2017: 1-4 - [c25]Francesco Centurelli
Class-AB current conveyors based on the FVF. ECCTD 2017: 1-4 - [c24]Francesco Centurelli
On the use of voltage conveyors for the synthesis of biquad filters and arbitrary networks. ECCTD 2017: 1-4 - 2016
- [j12]Francesco Centurelli
Comparative performance analysis and complementary triode based CMFB circuits for fully differential class AB symmetrical OTAs with low power consumption. Int. J. Circuit Theory Appl. 44(5): 1039-1054 (2016) - [c23]Francesco Centurelli
A new class-AB Flipped Voltage Follower using a common-gate auxiliary amplifier. MIXDES 2016: 143-146 - 2015
- [j11]Simone Bongiovanni, Francesco Centurelli
Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ICs from side-channel attacks. J. Cryptogr. Eng. 5(4): 269-288 (2015) - 2014
- [j10]Francesco Centurelli
A wideband amplifier topology based on positive capacitive feedback. Microelectron. J. 45(1): 50-58 (2014) - [c22]Francesco Centurelli
Design of broad-band power amplifiers by means of an impedance transforming lossy equalizer. MIXDES 2014: 189-193 - 2013
- [j9]Francesco Centurelli
Improved Digital Background Calibration of Time-Interleaved Pipeline A/D Converters. IEEE Trans. Circuits Syst. II Express Briefs 60-II(2): 86-90 (2013) - 2012
- [j8]Francesco Centurelli
Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(7): 1373-1383 (2012) - 2011
- [c21]Francesco Centurelli
An MDAC architecture with low sensitivity to finite opamp gain. ECCTD 2011: 568-571 - [c20]Francesco Centurelli
A class-AB flipped voltage follower output stage. ECCTD 2011: 757-760 - [c19]Francesco Centurelli
A class-AB very low voltage amplifier and sample & hold circuit. ECCTD 2011: 765-768 - [c18]Francesco Centurelli
A very low-voltage differential amplifier for opamp design. ECCTD 2011: 769-772 - 2010
- [j7]Francesco Centurelli
Behavioral Modeling for Calibration of Pipeline Analog-To-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(6): 1255-1264 (2010)
2000 – 2009
- 2009
- [j6]Francesco Centurelli
Design Solutions for Sample-and-Hold Circuits in CMOS Nanometer Technologies. IEEE Trans. Circuits Syst. II Express Briefs 56-II(6): 459-463 (2009) - 2008
- [j5]Francesco Centurelli
A Simple Technique for Fast Digital Background Calibration of A/D Converters. EURASIP J. Adv. Signal Process. 2008 (2008) - [c17]Francesco Centurelli
A gain-enhancing technique for very low-voltage amplifiers. ISCAS 2008: 2282-2285 - 2007
- [j4]Francesco Centurelli
A High-Speed Low-Voltage Phase Detector for Clock Recovery From NRZ Data. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(8): 1626-1635 (2007) - [j3]Francesco Centurelli
CMOS High-CMRR Current Output Stages. IEEE Trans. Circuits Syst. II Express Briefs 54-II(9): 745-749 (2007) - [c16]Francesco Centurelli
A Sample-and-Hold Circuit with Very Low Gain Error for Time Interleaving Applications. ECCTD 2007: 456-459 - [c15]Alfio Dario Grasso
CMOS Miller OTA with Body-Biased Output Stage. ECCTD 2007: 539-542 - [c14]Francesco Centurelli
Power-constrained Bandwidth Optimization in Cascaded Open-loop Amplifiers. ECCTD 2007: 651-654 - [c13]Francesco Centurelli
A distortion model for pipeline Analog-to-Digital converters. ISCAS 2007: 3387-3390 - [c12]Francesco Centurelli
A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations. PATMOS 2007: 516-525 - 2006
- [c11]Marco Balsi, Francesco Centurelli
Validation of a statistical non-linear model of GaAs HEMT MMIC's by hypothesis testing and principal components analysis. ISCAS 2006 - [c10]Francesco Centurelli
A model for the distortion due to switch on-resistance in sample-and-hold circuits. ISCAS 2006 - 2005
- [j2]Alberto Maria Bersani
Analytic transient solution of SCFL logic gates. Int. J. Circuit Theory Appl. 33(5): 365-378 (2005) - [j1]Francesco Centurelli
A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability. IEEE Trans. Very Large Scale Integr. Syst. 13(2): 191-200 (2005) - [c9]Francesco Centurelli
High-speed CMOS-to-ECL pad driver in 0.18µm CMOS. ISCAS (1) 2005: 448-451 - 2004
- [c8]Francesco Centurelli, Massimo Pozzoni, Giuseppe Scotti, Alessandro Trifiletti:
A high-speed low-voltage phase detector for clock recovery from NRZ data. ISCAS (4) 2004: 297-300 - [c7]Francesco Centurelli, Stefano Costi, Mauro Olivieri, Salvatore Pennisi, Alessandro Trifiletti:
Robust three-state PFD architecture with enhanced frequency acquisition capabilities. ISCAS (4) 2004: 812-815 - 2003
- [c6]Francesco Centurelli
Current output stage with improved CMRR. ICECS 2003: 543-546 - [c5]Marco Balsi, Francesco Centurelli
An accurate behavioral model of phase detectors for clock recovery circuits. ISCAS (4) 2003: 636-639 - 2002
- [c4]Marco Balsi
A tree-like amplifier architecture for large gain-bandwidth product. ICECS 2002: 121-124 - [c3]Marco Balsi
Bipolar differential cell with improved bandwidth performance. ICECS 2002: 1055-1058 - 2000
- [c2]Andrea Pallotta, Francesco Centurelli, Alessandro Trifiletti:
A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers. ISLPED 2000: 67-72
1990 – 1999
- 1998
- [c1]Andrea Pallotta, Francesco Centurelli
A monolithic 2.5-Gb/s clock and data recovery circuit based on Silicon bipolar technology. SYBEN 1998: 183-190
Coauthor Index
[c39] [c37] [j35] [j34] [j33] [j32] [j31] [j29] [c36] [c35] [c34] [c33] [j26] [j24] [j23] [j22] [j21] [c29] [j19] [j18] [j17] [j16] [j15] [c28] [j14] [j13] [c27] [c26] [c25] [c24] [j12] [c23] [j11] [j10] [c22] [j9] [j8] [c21] [c20] [c19] [c18] [j7] [j6] [j5] [c17] [j4] [j3] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [j2] [j1] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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last updated on 2024-10-07 21:19 CEST by the dblp team
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