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Toru Tanzawa
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2020 – today
- 2022
- [j23]Andrea Ballo
, Alfio Dario Grasso
A Charge Loss Aware Advanced Model of Dickson Voltage Multipliers. IEEE Access 10: 118082-118092 (2022) - [c18]Takuma Hashimoto, Toru Tanzawa
Antenna / On-Chip-Rectifier Co-Design Methodology for Micro-Watt Microwave Wireless Power Transfer. MWSCAS 2022: 1-4 - 2021
- [j22]Kazuki Matsuyama, Toru Tanzawa
A Circuit Analysis of Pre-Emphasis Pulses for RC Delay Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(6): 912-926 (2021) - [j21]Andrea Ballo
Charge Pumps for Ultra-Low-Power Applications: Analysis, Design, and New Solutions. IEEE Trans. Circuits Syst. II Express Briefs 68(8): 2895-2901 (2021) - 2020
- [j20]Andrea Ballo
Linear distribution of capacitance in Dickson charge pumps to reduce rise time. Int. J. Circuit Theory Appl. 48(4): 555-566 (2020) - [c17]Kazuma Koketsu, Toru Tanzawa
A Design of Cold Start Charge Pump for Flexible Thermoelectric Generator with High Output Impedance. ICECS 2020: 1-4
2010 – 2019
- 2019
- [c16]Kazuki Matsuyama, Toru Tanzawa
A Pre-Emphasis Pulse Generator Insensitive to Process Variation for Driving Large Memory and Panel Display Arrays with Minimal Delay Time. APCCAS 2019: 45-48 - [c15]Hayato Kawauchi, Toru Tanzawa
A 2V 3.8µW Fully-Integrated Clocked AC-DC Charge Pump with 0.5V 500Ω Vibration Energy Harvester. APCCAS 2019: 329-332 - [c14]Kazuki Matsuyama, Toru Tanzawa
Design of Pre-Emphasis Pulses for Large Memory Arrays with Minimal Word-Line Delay Time. ISCAS 2019: 1-5 - [c13]Shugo Tokuda, Toru Tanzawa
Toward a Minimum-Operating-Voltage Design of DC-DC Charge Pump Circuits for Energy Harvesting. ISCAS 2019: 1-4 - 2018
- [j19]Toru Tanzawa
Design Considerations on Power, Performance, Reliability and Yield in 3D NAND Technology. IEICE Trans. Electron. 101-C(1): 78-81 (2018) - [j18]Toru Tanzawa
On the Output Impedance and an Output Current-Power Efficiency Relationship of Dickson Charge Pump Circuits. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1664-1667 (2018) - 2017
- [j17]Toru Tanzawa
An Analytical Model of Charge Pump DC-DC Voltage Multiplier Using Diodes. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(5): 1137-1144 (2017) - [c12]Toru Tanzawa
On-chip switched-capacitor DC-DC converter in memory technology: State of the art and challenges. ECCTD 2017: 1-4 - 2016
- [j16]Toru Tanzawa
An Analytical Model of AC-DC Charge Pump Voltage Multipliers. IEICE Trans. Electron. 99-C(1): 108-118 (2016) - [c11]Toru Tanzawa
Design challenge in 3D NAND technology: A 4.8X area- and 1.3X power-efficient 20V charge pump using tier capacitors. A-SSCC 2016: 165-168 - [c10]Tomoharu Tanaka, Mark Helm, Tommaso Vali, Ramin Ghodsi, Koichi Kawai, Jae-Kwan Park, Shigekazu Yamada, Feng Pan, Yuichi Einaga, Ali Ghalam, Toru Tanzawa
7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory. ISSCC 2016: 142-144 - 2015
- [c9]Toru Tanzawa
An analytical model of multi-sine AC-DC voltage multiplier. ISCAS 2015: 1354-1357 - [c8]Toru Tanzawa
A comprehensive optimization methodology for designing charge pump voltage multipliers. ISCAS 2015: 1358-1361 - 2014
- [c7]Toru Tanzawa
An analytical model of AC-DC voltage multipliers. ICECS 2014: 323-326 - [c6]Toru Tanzawa
Design of DC-DC switched-capacitor voltage multiplier driven by DC energy transducer. ICECS 2014: 327-330 - 2012
- [j15]Toru Tanzawa
A Behavior Model of an On-Chip High Voltage Generator for Fast, System-Level Simulation. IEEE Trans. Very Large Scale Integr. Syst. 20(12): 2351-2355 (2012) - 2010
- [j14]Toru Tanzawa
A Behavior Model of a Dickson Charge Pump Circuit for Designing a Multiple Charge Pump System Distributed in LSIs. IEEE Trans. Circuits Syst. II Express Briefs 57-II(7): 527-530 (2010) - [j13]Toru Tanzawa
On Two-Phase Switched-Capacitor Multipliers With Minimum Circuit Area. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(10): 2602-2608 (2010) - [c5]Toru Tanzawa
A temperature compensation word-line voltage generator for multi-level cell NAND Flash memories. ESSCIRC 2010: 106-109
2000 – 2009
- 2009
- [c4]Toru Tanzawa
Dickson Charge Pump Circuit Design with Parasitic Resistance in Power Lines. ISCAS 2009: 1763-1766 - [c3]Raymond Zeng, Navneet Chalagalla, Dan Chu, Daniel Elmhurst, Matt Goldman, Chris Haid, Atif Huq, Takaaki Ichikawa, Joel Jorgensen, Owen Jungroth, Nishnat Kajla, Ravinder Kajley, Koichi Kawai, Jiro Kishimoto, Ali Madraswala, Tetsuji Manabe, Vikram Mehta, Midori Morooka, Katie Nguyen, Yoko Oikawa, Bharat Pathak, Rod Rozman, Tom Ryan, Andy Sendrowski, William Sheung, Martin Szwarc, Yasuhiro Takashima, Satoru Tamada, Toru Tanzawa
A 172mm2 32Gb MLC NAND flash memory in 34nm CMOS. ISSCC 2009: 236-237 - 2008
- [c2]Toru Tanzawa
A process- and temperature-tolerant power-on reset circuit with a flexible detection level higher than the bandgap voltage. ISCAS 2008: 2302-2305 - 2005
- [j12]Toru Tanzawa
A 2.4-GHz Temperature-Compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitters. IEICE Trans. Electron. 88-C(4): 490-495 (2005) - 2004
- [c1]Toru Tanzawa, Hiroyuki Shibayama, Ryota Terauchi, Katsumi Hisano, Hiroki Ishikuro, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Toru Takayama, Kenichi Agawa, Masayuki Koizumi, Fumitoshi Hatori:
A temperature-compensated CMOS LC-VCO enabling the direct modulation architecture in 2.4GHz GFSK transmitter. CICC 2004: 273-276 - 2002
- [j11]Toru Tanzawa
Circuit techniques for a 1.8-V-only NAND flash memory. IEEE J. Solid State Circuits 37(1): 84-89 (2002) - [j10]Toru Tanzawa
High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories. IEEE J. Solid State Circuits 37(10): 1318-1325 (2002) - [j9]Toru Tanzawa
A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller. IEEE J. Solid State Circuits 37(11): 1485-1492 (2002) - 2001
- [j8]Toru Tanzawa
Wordline voltage generating system for low-power low-voltage flash memories. IEEE J. Solid State Circuits 36(1): 55-63 (2001) - 2000
- [j7]Toru Tanzawa
Design of a sense circuit for low-voltage flash memories. IEEE J. Solid State Circuits 35(10): 1415-1421 (2000)
1990 – 1999
- 1999
- [j6]Hironori Banba, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba, Toru Tanzawa
A CMOS bandgap reference circuit with sub-1-V operation. IEEE J. Solid State Circuits 34(5): 670-674 (1999) - [j5]Toru Tanzawa
Optimization of word-line booster circuits for low-voltage flash memories. IEEE J. Solid State Circuits 34(8): 1091-1098 (1999) - 1998
- [j4]Ken Takeuchi, Tomoharu Tanaka, Toru Tanzawa
A multipage cell architecture for high-speed programming multilevel NAND flash memories. IEEE J. Solid State Circuits 33(8): 1228-1238 (1998) - 1997
- [j3]Toru Tanzawa
A compact on-chip ECC for low cost flash memories. IEEE J. Solid State Circuits 32(5): 662-669 (1997) - [j2]Toru Tanzawa
A stable programming pulse generator for single power supply flash memories. IEEE J. Solid State Circuits 32(6): 845-851 (1997) - [j1]Toru Tanzawa
A dynamic analysis of the Dickson charge pump circuit. IEEE J. Solid State Circuits 32(8): 1231-1240 (1997)
Coauthor Index
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