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Atsuo Hotta
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2000 – 2009
- 2000
- [j4]Takeshi Suzuki, Keiichi Higeta, Yasuhiro Fujimura, Kazumasa Ando, Hiroaki Nambu, Ryo Yamagata, Atsuo Hotta, Kunihiko Yamaguchi:
Synonym hit RAM - a 500-MHz CMOS SRAM macro with 576-bit parallel comparison and parity check functions. IEEE J. Solid State Circuits 35(2): 163-174 (2000) - [j3]Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kunihiko Yamaguchi, Noriyuki Homma, Atsuo Hotta:
Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz. IEEE J. Solid State Circuits 35(4): 564-571 (2000) - [j2]Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Kunihiko Yamaguchi, Atsuo Hotta, Noriyuki Homma:
A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM. IEEE J. Solid State Circuits 35(8): 1159-1168 (2000)
1990 – 1999
- 1999
- [j1]Toshiro Takahashi, Takashi Muto, Yuji Shirai, Fumihiko Shirotori, Yoshifumi Takada, Akira Yamagiwa, Akira Nishida, Atsuo Hotta, Tadashi Kiyuna:
110-GB/s simultaneous bidirectional transceiver logic synchronized with a system clock. IEEE J. Solid State Circuits 34(11): 1526-1533 (1999)
1980 – 1989
- 1989
- [c2]Hideo Maejima, Tadaaki Bandoh, Yoji Nishio, Tadashi Fukushima, Masanori Odaka, Atsuo Hotta:
Circuit technologies for BiCMOS VLSI's as computer elements. ICCD 1989: 318-321 - [c1]Yasuhiro Nakatsuka, Takashi Hotta, Shigeya Tanaka, Tadaaki Bandoh, Ryuichi Satomura, Syuichi Nakagami, Tetsuo Nakano, Atsuo Hotta, Takashi Moriyama, Shigemi Adachi, Shoji Iwamoto:
A high performance BiCMOS 32-bit microprocessor. ICCD 1989: 358-361
Coauthor Index
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