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Hideo Maejima
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2010 – 2019
- 2011
- [j4]Osamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada
, Keiji Kimura, Hironori Kasahara
A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core. IEICE Trans. Electron. 94-C(4): 663-669 (2011) - 2010
- [c5]Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno
A 45nm 37.3GOPS/W heterogeneous multi-core SoC. ISSCC 2010: 100-101
2000 – 2009
- 2009
- [j3]Tohru Nojiri, Yuki Kondo, Naohiko Irie, Masayuki Ito, Hajime Sasaki, Hideo Maejima:
Domain Partitioning Technology for Embedded Multicore Processors. IEEE Micro 29(6): 7-17 (2009) - [c4]Yoshitaka Arahori, Katsuhiko Gondow, Hideo Maejima:
TCBC: Trap Caching Bounds Checking for C. DASC 2009: 49-56
1990 – 1999
- 1991
- [j2]Nobuyasu Kanekawa, Hideo Maejima, Hatsuhiko Kato, Hirokazu Ihara:
Fault-tolerant computer system with stepwise negotiating voting. Syst. Comput. Jpn. 22(2): 1-9 (1991)
1980 – 1989
- 1989
- [c3]Nobuyasu Kanekawa, Hideo Maejima, Hatsuhiko Kato, Hirokazu Ihara:
Dependable onboard computer systems with a new method-stepwise negotiating voting. FTCS 1989: 13-19 - [c2]Hideo Maejima, Tadaaki Bandoh, Yoji Nishio, Tadashi Fukushima, Masanori Odaka, Atsuo Hotta:
Circuit technologies for BiCMOS VLSI's as computer elements. ICCD 1989: 318-321 - 1986
- [c1]Hideo Maejima, Hiroyuki Kida, Tan Watanabe, Shiro Baba, Keiichi Kurakazu:
A 16-Bit Microprocessor with Multi-Register Bank Architecture. FJCC 1986: 1014-1018 - 1983
- [j1]Hideo Maejima, Koyo Katsura, Hideo Nakamura, Toshimasa Kihara:
The VLSI Control Structure of a CMOS Microcomputer. IEEE Micro 3(6): 9-16 (1983)
Coauthor Index
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