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Jude Haris
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2020 – today
- 2024
- [c2]Nicolas Bohm Agostini
, Jude Haris, Perry Gibson, Malith Jayaweera, Norm Rubin, Antonino Tumeo, José L. Abellán, José Cano, David R. Kaeli:
AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators. CGO 2024: 143-157 - [i5]Jude Haris, Nicolas Bohm Agostini
Data Transfer Optimizations for Host-CPU and Accelerators in AXI4MLIR. CoRR abs/2402.19184 (2024) - [i4]Jude Haris, Rappy Saha, Wenhao Hu, José Cano:
Designing Efficient LLM Accelerators for Edge Devices. CoRR abs/2408.00462 (2024) - [i3]Rappy Saha, Jude Haris, José Cano:
Accelerating PoT Quantization on Edge Devices. CoRR abs/2409.20403 (2024) - 2023
- [j1]Jude Haris
SECDA-TFLite: A toolkit for efficient development of FPGA-based DNN accelerators for edge inference. J. Parallel Distributed Comput. 173: 140-151 (2023) - [i2]Nicolas Bohm Agostini, Jude Haris, Perry Gibson, Malith Jayaweera, Norm Rubin, Antonino Tumeo, José L. Abellán, José Cano, David R. Kaeli:
AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators. CoRR abs/2312.14821 (2023) - 2021
- [c1]Jude Haris
SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN Accelerators for Edge Inference. SBAC-PAD 2021: 33-43 - [i1]Jude Haris, Perry Gibson, José Cano, Nicolas Bohm Agostini, David R. Kaeli:
SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN Accelerators for Edge Inference. CoRR abs/2110.00478 (2021)
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last updated on 2024-10-22 20:11 CEST by the dblp team
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