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Sourav Das 0002
Person information
- affiliation: Intel Corporation, Santa Clara, CA, USA
- affiliation (PhD 2018): Washington State University, School of Electrical Engineering and Computer Science, Pullman, WA, USA
Other persons with the same name
- Sourav Das — disambiguation page
- Sourav Das 0001
— University of Illinois at Urbana Champaign, Siebel School of Computing and Data Science, Champaign, IL, USA (and 1 more)
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2020 – today
- 2020
- [j9]Sourav Das
Testing of Prebond Through Silicon Vias. IEEE Des. Test 37(4): 27-34 (2020) - [j8]Srinivasan Gopal
A Hybrid 3D Interconnect With 2x Bandwidth Density Employing Orthogonal Simultaneous Bidirectional Signaling for 3D NoC. IEEE Trans. Circuits Syst. 67-I(11): 3919-3932 (2020)
2010 – 2019
- 2019
- [j7]Dongjin Lee, Sourav Das, Partha Pratim Pande:
Analyzing power-thermal-performance trade-offs in a high-performance 3D NoC architecture. Integr. 65: 282-292 (2019) - [j6]Dongjin Lee, Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty
Impact of Electrostatic Coupling on Monolithic 3D-enabled Network on Chip. ACM Trans. Design Autom. Electr. Syst. 24(6): 62:1-62:22 (2019) - [c12]Sourav Das, Fei Su, Sreejit Chakravarty:
A Comparative Study of Pre-bond TSV Test Methodologies. VTS 2019: 1-6 - 2018
- [j5]Dongjin Lee, Sourav Das, Dae Hyun Kim, Janardhan Rao Doppa, Partha Pratim Pande
Design Space Exploration of 3D Network-on-Chip: A Sensitivity-based Optimization Approach. ACM J. Emerg. Technol. Comput. Syst. 14(3): 32:1-32:26 (2018) - [j4]Dongjin Lee, Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty
Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip. ACM Trans. Design Autom. Electr. Syst. 23(5): 60:1-60:25 (2018) - [j3]Srinivasan Gopal
High-Performance and Small-Form Factor Near-Field Inductive Coupling for 3-D NoC. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2921-2934 (2018) - [c11]Sourav Das, Fei Su, Sreejit Chakravarty:
A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing. ITC 2018: 1-10 - [c10]Sourav Das, Kanad Basu, Janardhan Rao Doppa, Partha Pratim Pande, Ramesh Karri
Abetting Planned Obsolescence by Aging 3D Networks-on-Chip. NOCS 2018: 10:1-10:8 - 2017
- [j2]Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty
Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(5): 719-732 (2017) - [j1]Sourav Das, Dongjin Lee, Wonje Choi, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty
VFI-Based Power Management to Enhance the Lifetime of High-Performance 3D NoCs. ACM Trans. Design Autom. Electr. Syst. 23(1): 7:1-7:26 (2017) - [c9]Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty
Robust TSV-based 3D NoC design to counteract electromigration and crosstalk noise. DATE 2017: 1366-1371 - [c8]Sourav Das, Srinivasan Gopal
Energy-efficient and robust 3D NoCs with contactless vertical links (Invited paper). ICCAD 2017: 1-6 - [c7]Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty
Monolithic 3D-Enabled High Performance and Energy Efficient Network-on-Chip. ICCD 2017: 233-240 - [c6]Dongjin Lee, Sourav Das, Partha Pratim Pande:
Performance-thermal trade-offs for a VFI-enabled 3D NoC architecture. ISQED 2017: 271-276 - [c5]Srinivasan Gopal
Energy and Area Efficient Near Field Inductive Coupling: A Case Study on 3D NoC. NOCS 2017: 5:1-5:8 - 2016
- [c4]Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty:
Reliability and performance trade-offs for 3D NoC-enabled multicore chips. DATE 2016: 1429-1432 - [c3]Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty
Energy-efficient and reliable 3D network-on-chip (NoC): architectures and optimization algorithms. ICCAD 2016: 57 - [i1]Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty:
Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3D Small-world Network-on-Chip. CoRR abs/1608.06972 (2016) - 2015
- [c2]Sourav Das, Dongjin Lee, Dae Hyun Kim, Partha Pratim Pande:
Small-World Network Enabled Energy Efficient and Robust 3D NoC Architectures. ACM Great Lakes Symposium on VLSI 2015: 133-138 - [c1]Sourav Das, Janardhan Rao Doppa, Daehyun Kim, Partha Pratim Pande, Krishnendu Chakrabarty
Optimizing 3D NoC Design for Energy Efficiency: A Machine Learning Approach. ICCAD 2015: 705-712
Coauthor Index
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