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Srinivasan Gopal
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2020 – today
- 2021
- [j9]Natarajan Shanmugam
, Srinivasan Gopal
Diagnosis of Inter-Turn Shorts of Loaded Transformer Under Various Load Currents and Power Factors; Impulse Voltage-Based Frequency Response Approach. IEEE Access 9: 40811-40822 (2021) - [c6]Jainaveen Sundaram, Srinivasan Gopal
A Reconfigurable Asynchronous SERDES for Heterogenous Chiplet Interconnects. ISQED 2021: 542-546 - [c5]Srivatsa Srinivasa, Akshay Krishna Ramanathan, Jainaveen Sundaram, Dileep Kurian, Srinivasan Gopal
Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation. ISQED 2021: 547-552 - 2020
- [j8]Aqeeb Iqbal Arka
Making a Case for Partially Connected 3D NoC: NFIC versus TSV. ACM J. Emerg. Technol. Comput. Syst. 16(4): 41:1-41:17 (2020) - [j7]Srinivasan Gopal
A Hybrid 3D Interconnect With 2x Bandwidth Density Employing Orthogonal Simultaneous Bidirectional Signaling for 3D NoC. IEEE Trans. Circuits Syst. 67-I(11): 3919-3932 (2020)
2010 – 2019
- 2019
- [j6]Sheikh Nijam Ali
A 25-35 GHz Neutralized Continuous Class-F CMOS Power Amplifier for 5G Mobile Communications Achieving 26% Modulation PAE at 1.5 Gb/s and 46.4% Peak PAE. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2): 834-847 (2019) - [j5]Luke Renaud
Analysis of Systematic Losses in Hybrid Envelope Tracking Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(4): 1319-1330 (2019) - [c4]Srinivasan Gopal, Deukhyoun Heo, Tanay Karnik:
Hierarchical Design Methodology and Optimization for Proximity Communication based Contactless 3D ThruChip Interface. 3DIC 2019: 1-6 - 2018
- [j4]Srinivasan Gopal
A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 506-518 (2018) - [j3]Joe Baylon, Xinmin Yu, Srinivasan Gopal
A 16-Gb/s Low-Power Inductorless Wideband Gain-Boosted Baseband Amplifier With Skewed Differential Topology for Wireless Network-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2406-2418 (2018) - [j2]Srinivasan Gopal
High-Performance and Small-Form Factor Near-Field Inductive Coupling for 3-D NoC. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2921-2934 (2018) - [c3]Sheikh Nijam Ali
A 28GHz 41%-PAE linear CMOS power amplifier using a transformer-based AM-PM distortion-correction technique for 5G phased arrays. ISSCC 2018: 406-408 - 2017
- [c2]Sourav Das, Srinivasan Gopal
Energy-efficient and robust 3D NoCs with contactless vertical links (Invited paper). ICCAD 2017: 1-6 - [c1]Srinivasan Gopal
Energy and Area Efficient Near Field Inductive Coupling: A Case Study on 3D NoC. NOCS 2017: 5:1-5:8
2000 – 2009
- 2009
- [j1]Srinivasan Gopal, Ying-Cheng Lai:
Inducing Chaos in MOSFET-Based Electronic Circuits. Circuits Syst. Signal Process. 28(4): 535-545 (2009)
Coauthor Index
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