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Sreenivas Subramoney
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2020 – today
- 2024
- [j7]Can Firtina
, Kamlesh R. Pillai
ApHMM: Accelerating Profile Hidden Markov Models for Fast and Energy-efficient Genome Analysis. ACM Trans. Archit. Code Optim. 21(1): 19:1-19:29 (2024) - [c45]Rahul Bera, Adithya Ranganathan, Joydeep Rakshit, Sujit Mahto, Anant V. Nori, Jayesh Gaur, Ataberk Olgun, Konstantinos Kanellopoulos, Mohammad Sadrosadati, Sreenivas Subramoney, Onur Mutlu:
Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution. ISCA 2024: 88-102 - [c44]Alan Nair, Sandeep Kumar, Aravinda Prasad, Ying Huang, Andy Rudoff, Sreenivas Subramoney:
Telescope: Telemetry for Gargantuan Memory Footprint Applications. USENIX ATC 2024: 409-424 - [i21]Souvik Kundu, Anthony Sarah, Vinay Joshi, Om Ji Omer, Sreenivas Subramoney:
CiMNet: Towards Joint Optimization for DNN Architecture and Configuration for Compute-In-Memory Hardware. CoRR abs/2402.11780 (2024) - [i20]Sandeep Kumar, Aravinda Prasad, Sreenivas Subramoney:
Taming Server Memory TCO with Multiple Software-Defined Compressed Tiers. CoRR abs/2404.13886 (2024) - [i19]Vinay Joshi, Prashant Laddha, Shambhavi Sinha
QCQA: Quality and Capacity-aware grouped Query Attention. CoRR abs/2406.10247 (2024) - [i18]Rahul Bera, Adithya Ranganathan, Joydeep Rakshit, Sujit Mahto, Anant V. Nori, Jayesh Gaur, Ataberk Olgun, Konstantinos Kanellopoulos, Mohammad Sadrosadati, Sreenivas Subramoney, Onur Mutlu:
Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution. CoRR abs/2406.18786 (2024) - [i17]Rajat Jain, Aravinda Prasad, Sreenivas Subramoney, Arkaprava Basu:
iMIV: in-Memory Integrity Verification for NVM. CoRR abs/2407.09180 (2024) - 2023
- [j6]Raghav Singhal
Enhanced regularization for on-chip training using analog and temporary memory weights. Neural Networks 165: 1050-1057 (2023) - [c43]Geonhwa Jeong, Sana Damani, Abhimanyu Rajeshkumar Bambhaniya
VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs. HPCA 2023: 259-272 - [i16]Geonhwa Jeong, Sana Damani, Abhimanyu Rajeshkumar Bambhaniya, Eric Qin, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna:
VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs. CoRR abs/2302.08687 (2023) - [i15]Quintin Fettes
Reclaimer: A Reinforcement Learning Approach to Dynamic Resource Allocation for Cloud Microservices. CoRR abs/2304.07941 (2023) - [i14]Shivank Garg, Aravinda Prasad, Debadatta Mishra, Sreenivas Subramoney:
Motivating Next-Generation OS Physical Memory Management for Terabyte-Scale NVMMs. CoRR abs/2310.03370 (2023) - [i13]Alan Nair, Sandeep Kumar, Aravinda Prasad, Andy Rudoff, Sreenivas Subramoney:
Telescope: Telemetry at Terabyte Scale. CoRR abs/2311.10275 (2023) - 2022
- [j5]Biji George
A Unified Programmable Edge Matrix Processor for Deep Neural Networks and Matrix Algebra. ACM Trans. Embed. Comput. Syst. 21(5): 63:1-63:30 (2022) - [j4]Sparsh Mittal
A Survey of Deep Learning on CPUs: Opportunities and Co-Optimizations. IEEE Trans. Neural Networks Learn. Syst. 33(10): 5095-5115 (2022) - [c42]Anirud Thyagharajan, Benjamin Ummenhofer, Prashant Laddha, Om Ji Omer, Sreenivas Subramoney:
Segment-Fusion: Hierarchical Context Fusion for Robust 3D Semantic Segmentation. CVPR 2022: 1226-1235 - [c41]Sudhanshu Shukla, Sumeet Bandishte, Jayesh Gaur, Sreenivas Subramoney:
Register file prefetching. ISCA 2022: 410-423 - [c40]Damla Senol Cali, Konstantinos Kanellopoulos, Joël Lindegger, Zülal Bingöl, Gurpreet S. Kalsi, Ziyi Zuo, Can Firtina, Meryem Banu Cavlak, Jeremie S. Kim, Nika Mansouri-Ghiasi, Gagandeep Singh, Juan Gómez-Luna, Nour Almadhoun Alserr, Mohammed Alser, Sreenivas Subramoney, Can Alkan, Saugata Ghose, Onur Mutlu:
SeGraM: a universal hardware accelerator for genomic sequence-to-graph and sequence-to-sequence mapping. ISCA 2022: 638-655 - [c39]Shixin Song, Tanvir Ahmed Khan
Thermometer: profile-guided btb replacement for data center applications. ISCA 2022: 742-756 - [c38]Pramod Kumar Bharti, Saurabh Jain, Kamlesh R. Pillai, Sagar Varma Sayyaparaju, Gurpreet S. Kalsi, Joycee Mekie, Sreenivas Subramoney:
Compute-In-Memory Using 6T SRAM for a Wide Variety of Workloads. ISCAS 2022: 2963-2967 - [c37]Logan Moody, Wei Qi, Abdolrasoul Sharifi, Layne Berry, Joey Rudek, Jayesh Gaur, Jeff Parkhurst, Sreenivas Subramoney, Kevin Skadron
Speculative Code Compaction: Eliminating Dead Code via Speculative Microcode Transformations. MICRO 2022: 162-180 - [c36]Ashwin Sanjay Lele, Srivatsava Jandhyala
Disrupting Low-Write-Energy vs. Fast-Read Dilemma in RRAM to Enable L1 Instruction Cache. VDAT 2022: 499-512 - [i12]Damla Senol Cali, Konstantinos Kanellopoulos, Joël Lindegger, Zülal Bingöl, Gurpreet S. Kalsi, Ziyi Zuo, Can Firtina, Meryem Banu Cavlak, Jeremie S. Kim, Nika Mansouri-Ghiasi, Gagandeep Singh, Juan Gómez-Luna, Nour Almadhoun Alserr, Mohammed Alser, Sreenivas Subramoney, Can Alkan, Saugata Ghose, Onur Mutlu:
SeGraM: A Universal Hardware Accelerator for Genomic Sequence-to-Graph and Sequence-to-Sequence Mapping. CoRR abs/2205.05883 (2022) - [i11]Dipan Mandal, Abhilash Jain, Sreenivas Subramoney:
Unsupervised Learning of Depth, Camera Pose and Optical Flow from Monocular Video. CoRR abs/2205.09821 (2022) - [i10]Can Firtina, Kamlesh R. Pillai, Gurpreet S. Kalsi, Bharathwaj Suresh, Damla Senol Cali, Jeremie S. Kim, Taha Shahroodi, Meryem Banu Cavlak, Joël Lindegger, Mohammed Alser, Juan Gómez-Luna, Sreenivas Subramoney, Onur Mutlu:
ApHMM: Accelerating Profile Hidden Markov Models for Fast and Energy-Efficient Genome Analysis. CoRR abs/2207.09765 (2022) - 2021
- [c35]Geonhwa Jeong, Eric Qin, Ananda Samajdar, Christopher J. Hughes
RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU. DAC 2021: 253-258 - [c34]C. N. Ramachandra, Anirban Nag, Rajeev Balasubramonian, Gurpreet S. Kalsi, Kamlesh R. Pillai, Sreenivas Subramoney:
ONT-X: An FPGA Approach to Real-time Portable Genomic Analysis. FCCM 2021: 268-269 - [c33]Anant V. Nori, Rahul Bera
REDUCT: Keep it Close, Keep it Cool! : Efficient Scaling of DNN Inference on Multi-core CPUs with Near-Cache Compute. ISCA 2021: 167-180 - [c32]Sandeep Kumar, Aravinda Prasad, Smruti R. Sarangi, Sreenivas Subramoney:
Radiant: efficient page table management for tiered memory systems. ISMM 2021: 66-79 - [c31]Michael LeMay
Cryptographic Capability Computing. MICRO 2021: 253-267 - [c30]Niranjan K. Soundararajan, Peter Braun, Tanvir Ahmed Khan
PDede: Partitioned, Deduplicated, Delta Branch Target Buffer. MICRO 2021: 779-791 - [c29]Tanvir Ahmed Khan
Twig: Profile-Guided BTB Prefetching for Data Center Applications. MICRO 2021: 816-829 - [c28]Rahul Bera
Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning. MICRO 2021: 1121-1137 - [i9]Sandeep Kumar, Aravinda Prasad, Smruti R. Sarangi, Sreenivas Subramoney:
Page Table Management for Heterogeneous Memory Systems. CoRR abs/2103.10779 (2021) - [i8]Rahul Bera, Konstantinos Kanellopoulos, Anant V. Nori, Taha Shahroodi, Sreenivas Subramoney, Onur Mutlu:
Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning. CoRR abs/2109.12021 (2021) - [i7]Geonhwa Jeong, Eric Qin, Ananda Samajdar, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna:
RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU. CoRR abs/2110.01752 (2021) - [i6]Anirud Thyagharajan, Benjamin Ummenhofer, Prashant Laddha, Om Ji Omer, Sreenivas Subramoney:
Robust 3D Scene Segmentation through Hierarchical and Learnable Part-Fusion. CoRR abs/2111.08434 (2021) - 2020
- [j3]Sakshi Tiwari
REAL: REquest Arbitration in Last Level Caches. ACM Trans. Embed. Comput. Syst. 18(6): 115:1-115:24 (2020) - [c27]Saurabh Gupta, Niranjan Soundararajan, Ragavendra Natarajan, Sreenivas Subramoney
Opportunistic Early Pipeline Re-steering for Data-dependent Branches. PACT 2020: 305-316 - [c26]Nagadastagiri Challapalle, Sahithi Rampalli, Makesh Chandran, Gurpreet S. Kalsi, Sreenivas Subramoney
PSB-RNN: A Processing-in-Memory Systolic Array Architecture using Block Circulant Matrices for Recurrent Neural Networks. DATE 2020: 180-185 - [c25]Prashant Laddha, Om Ji Omer, Gurpreet Singh Kalsi, Dipan Kumar Mandal, Sreenivas Subramoney:
Descriptor Scoring for Feature Selection in Real-Time Visual Slam. ICIP 2020: 2601-2605 - [c24]Anirud Thyagharajan, Om Ji Omer, Dipan Mandal, Sreenivas Subramoney
Towards Noise Resilient SLAM. ICRA 2020: 72-79 - [c23]Sumeet Bandishte, Jayesh Gaur, Zeev Sperber, Lihu Rappoport, Adi Yoaz, Sreenivas Subramoney
Focused Value Prediction. ISCA 2020: 79-91 - [c22]Adarsh Chauhan, Jayesh Gaur, Zeev Sperber, Franck Sala, Lihu Rappoport, Adi Yoaz, Sreenivas Subramoney
Auto-Predication of Critical Branches. ISCA 2020: 92-104 - [c21]Antara Ganguly, Shankar Balachandran, Anant V. Nori, Virendra Singh, Sreenivas Subramoney
Characterization of Data Generating Neural Network Applications on x86 CPU Architecture. ISPASS 2020: 121-122 - [c20]Akshay Krishna Ramanathan, Gurpreet S. Kalsi, Srivatsa Srinivasa, Tarun Makesh Chandran, Kamlesh R. Pillai, Om Ji Omer, Vijaykrishnan Narayanan
Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration. MICRO 2020: 88-101 - [c19]Damla Senol Cali
GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis. MICRO 2020: 951-966 - [i5]Damla Senol Cali, Gurpreet S. Kalsi, Zülal Bingöl, Can Firtina, Lavanya Subramanian, Jeremie S. Kim, Rachata Ausavarungnirun, Mohammed Alser, Juan Gómez-Luna, Amirali Boroumand, Anant Nori, Allison Scibisz, Sreenivas Subramoney, Can Alkan, Saugata Ghose, Onur Mutlu:
GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis. CoRR abs/2009.07692 (2020) - [i4]Anant V. Nori, Rahul Bera
Proximu: Efficiently Scaling DNN Inference in Multi-core CPUs through Near-Cache Compute. CoRR abs/2011.11695 (2020) - [i3]Om Ji Omer, Prashant Laddha, Gurpreet S. Kalsi, Anirud Thyagharajan, Kamlesh R. Pillai, Abhimanyu Kulkarni, Anbang Yao, Yurong Chen, Sreenivas Subramoney:
AccSS3D: Accelerator for Spatially Sparse 3D DNNs. CoRR abs/2011.12669 (2020)
2010 – 2019
- 2019
- [c18]Dipan Kumar Mandal, Srivatsava Jandhyala, Om Ji Omer, Gurpreet S. Kalsi, Biji George, Gopi Neela, Santhosh Kumar Rethinagiri, Sreenivas Subramoney
Visual Inertial Odometry At the Edge: A Hardware-Software Co-design Approach for Ultra-low Latency and Power. DATE 2019: 960-963 - [c17]Mainak Chaudhuri, Jayesh Gaur, Sreenivas Subramoney
Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth. ICCD 2019: 109-118 - [c16]Niranjan Soundararajan, Saurabh Gupta, Ragavendra Natarajan, Jared Stark, Rahul Pal, Franck Sala, Lihu Rappoport, Adi Yoaz, Sreenivas Subramoney
Towards the adoption of Local Branch Predictors in Modern Out-of-Order Superscalar Processors. MICRO 2019: 519-530 - [c15]Rahul Bera
DSPatch: Dual Spatial Pattern Prefetcher. MICRO 2019: 531-544 - [i2]Rahul Bera, Anant V. Nori, Onur Mutlu, Sreenivas Subramoney:
DSPatch: Dual Spatial Pattern Prefetcher. CoRR abs/1910.03075 (2019) - 2018
- [c14]Lavanya Subramanian, Kaushik Vaidyanathan, Anant Nori, Sreenivas Subramoney
Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems. DAC 2018: 170:1-170:6 - [c13]Anant Nori, Jayesh Gaur, Siddharth Rai
Criticality Aware Tiered Cache Hierarchy: A Fundamental Relook at Multi-Level Cache Hierarchies. ISCA 2018: 96-109 - [c12]Kunal Korgaonkar, Ishwar Bhati, Huichu Liu, Jayesh Gaur, Sasikanth Manipatruni, Sreenivas Subramoney
Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache. ISCA 2018: 315-327 - [c11]Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney
Tackling memory access latency through DRAM row management. MEMSYS 2018: 137-147 - [i1]Ishwar Bhati, Udit Dhawan, Jayesh Gaur, Sreenivas Subramoney, Hong Wang:
MARS: Memory Aware Reordered Source. CoRR abs/1808.03518 (2018) - 2017
- [j2]Mainak Chaudhuri, Mukesh Agrawal, Jayesh Gaur, Sreenivas Subramoney
Micro-Sector Cache: Improving Space Utilization in Sectored DRAM Caches. ACM Trans. Archit. Code Optim. 14(1): 7:1-7:29 (2017) - [j1]Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney
Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip Network. ACM Trans. Archit. Code Optim. 14(4): 32:1-32:25 (2017) - [c10]Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney
A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioning. DATE 2017: 800-805 - [c9]Jayesh Gaur, Mainak Chaudhuri, Pradeep Ramachandran, Sreenivas Subramoney
Near-Optimal Access Partitioning for Memory Hierarchies with Multiple Heterogeneous Bandwidth Sources. HPCA 2017: 13-24 - 2016
- [c8]Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney:
Machine Learned Machines: Adaptive co-optimization of caches, cores, and On-chip Network. DATE 2016: 253-256 - [c7]Jayesh Gaur, Alaa R. Alameldeen, Sreenivas Subramoney
Base-Victim Compression: An Opportunistic Cache Compression Architecture. ISCA 2016: 317-328 - 2014
- [c6]Preeti Ranjan Panda, Namita Sharma, Arun Kumar Pilania, Gummidipudi Krishnaiah, Sreenivas Subramoney
Array scalarization in high level synthesis. ASP-DAC 2014: 622-627 - 2013
- [c5]Jayesh Gaur, Raghuram Srinivasan, Sreenivas Subramoney
Efficient management of last-level caches in graphics processors for 3D scene rendering workloads. MICRO 2013: 395-407 - 2012
- [c4]Mainak Chaudhuri, Jayesh Gaur, Nithiyanandan Bashyam, Sreenivas Subramoney
Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches. PACT 2012: 293-304 - 2011
- [c3]Jayesh Gaur, Mainak Chaudhuri, Sreenivas Subramoney
Bypass and insertion algorithms for exclusive last-level caches. ISCA 2011: 81-92
2000 – 2009
- 2004
- [c2]Ali-Reza Adl-Tabatabai, Richard L. Hudson, Mauricio J. Serrano, Sreenivas Subramoney
Prefetch inection based on hardware monitoring and object metadata. PLDI 2004: 267-276 - 2000
- [c1]Richard L. Hudson, J. Eliot B. Moss, Sreenivas Subramoney
Cycles to Recycle: Garbage Collection on the IA-64. ISMM 2000: 101-110
Coauthor Index
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last updated on 2024-10-07 21:24 CEST by the dblp team
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