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Jeanine E. Cook
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2020 – today
- 2022
- [j11]Bobin Deng
, Sriseshan Srikanth
Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems. IEEE Trans. Computers 71(3): 613-627 (2022) - 2021
- [j10]Daniel Dunning
A Performance Analysis of Phantom-Cell Adaptive Mesh Refinement on CPUs and GPUs. J. Comput. Inf. Sci. Eng. 21(1) (2021) - [j9]Sriseshan Srikanth
SortCache: Intelligent Cache Management for Accelerating Sparse Data Workloads. ACM Trans. Archit. Code Optim. 18(4): 56:1-56:24 (2021) - 2020
- [j8]Sriseshan Srikanth
MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams. ACM Trans. Archit. Code Optim. 16(4): 35:1-35:26 (2020) - [c32]Richard F. Barrett, Jeanine E. Cook, Stephen L. Olivier, Omar Aaziz, Christipher D. Jenkins, Courtenay T. Vaughan:
Exploring Chapel Productivity Using Some Graph Algorithms. IPDPS Workshops 2020: 672
2010 – 2019
- 2019
- [c31]Omar Aaziz, Jeanine E. Cook, Courtenay Vaughan, David Richards:
Proxy or Imposter? A Method and Case Study to Determine the Answer. CLUSTER 2019: 1-9 - [c30]Omar Aaziz, Courtenay Vaughan, Jonathan E. Cook, Jeanine E. Cook, Jeffery Kuehn, David Richards:
Fine-Grained Analysis of Communication Similarity between Real and Proxy Applications. PMBS@SC 2019: 93-102 - 2018
- [j7]Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Thomas M. Conte
Extending Moore's Law via Computationally Error-Tolerant Computing. ACM Trans. Archit. Code Optim. 15(1): 8:1-8:27 (2018) - [j6]Nafiul Alam Siddique
A performance study of the time-varying cache behavior: a study on APEX, Mantevo, NAS, and PARSEC. J. Supercomput. 74(2): 665-695 (2018) - [c29]Omar Aaziz, Jeanine E. Cook, Jonathan Cook, Tanner Juedeman, David Richards, Courtenay Vaughan:
A Methodology for Characterizing the Correspondence Between Real and Proxy Applications. CLUSTER 2018: 190-200 - [c28]Sriseshan Srikanth, Paul G. Rabbat, Eric R. Hein, Bobin Deng, Thomas M. Conte
Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures. HPCA 2018: 696-709 - [c27]Omar Aaziz, Jeanine E. Cook, Jonathan E. Cook, Courtenay Vaughan:
Exploring and Quantifying How Communication Behaviors in Proxies Relate to Real Applications. PMBS@SC 2018: 12-22 - 2017
- [j5]Li Tang
PeaPaw: Performance and Energy-Aware Partitioning of Workload on Heterogeneous Platforms. ACM Trans. Design Autom. Electr. Syst. 22(3): 41:1-41:26 (2017) - [c26]Mohammad A. Qayum
StAdHyTM: A Statically Adaptive Hybrid Transactional Memory: A scalability study on large parallel graphs. CCWC 2017: 1-7 - [c25]Mohammad A. Qayum, Abdel-Hameed A. Badawy, Jeanine E. Cook:
Analyzing Hybrid Transactional Memory Performance Using Intel SDE. CLUSTER 2017: 627-628 - [c24]Erik P. DeBenedictis, Jeanine E. Cook, Sriseshan Srikanth, Thomas M. Conte
Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C. HPEC 2017: 1-7 - [c23]Sriseshan Srikanth, Thomas M. Conte
The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing. ICRC 2017: 1-8 - [c22]Nafiul Alam Siddique
LMStr: exploring shared hardware controlled scratchpad memory for multicores. MEMSYS 2017: 152-165 - [c21]Mohammad A. Qayum, Abdel-Hameed A. Badawy, Jeanine E. Cook:
DyAdHyTM: a low overhead dynamically adaptive hybrid transactional memory with application to large graphs. MEMSYS 2017: 327-336 - [c20]Xingfu Wu
Performance and Power Characteristics and Optimizations of Hybrid MPI/OpenMP LULESH Miniapps under Various Workloads. E2SC@SC 2017: 4:1-4:8 - [c19]Mohammad Qayum, Abdel-Hameed A. Badawy, Jeanine E. Cook:
DAdHTM: Low overhead dynamically adaptive hardware transactional memory for large graphs a scalability study. SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI 2017: 1-8 - [c18]Nafiul Alam Siddique
Local memory store (LMStr): A hardware controlled shared scratchpad for multicores. SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI 2017: 1-6 - [i1]Mohammad Qayum, Abdel-Hameed A. Badawy, Jeanine E. Cook:
DyAdHyTM: A Low Overhead Dynamically Adaptive Hybrid Transactional Memory on Big Data Graphs. CoRR abs/1702.07081 (2017) - 2016
- [j4]Xingfu Wu
Using Performance-Power Modeling to Improve Energy Efficiency of HPC Applications. Computer 49(10): 20-29 (2016) - [c17]Sapan Agarwal
Energy efficiency limits of logic and memory. ICRC 2016: 1-8 - [c16]Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte
Computationally-redundant energy-efficient processing for y'all (CREEPY). ICRC 2016: 1-8 - [c15]Nafiul Alam Siddique
LMStr: Local memory store the case for hardware controlled scratchpad memory for general purpose processors. IPCCC 2016: 1-8 - [c14]Patricia Grubel
Using Intrinsic Performance Counters to Assess Efficiency in Task-Based Parallel Applications. IPDPS Workshops 2016: 1692-1701 - 2015
- [c13]Patricia Grubel
The Performance Implication of Task Size for Applications on the HPX Runtime System. CLUSTER 2015: 682-689 - [c12]Erik P. DeBenedictis, Jeanine E. Cook, Mark Hoemmen, Tzevetan S. Metodi:
Optimal adiabatic scaling and the processor-in-memory-and-storage architecture (OAS+PIMS). NANOARCH 2015: 69-74 - 2014
- [c11]Waleed Alkohlani, Jeanine E. Cook, Jonathan E. Cook:
Accurate statistical performance modeling and validation of out-of-order processors using Monte Carlo methods. IPCCC 2014: 1-10 - [c10]James A. Ang, Richard F. Barrett, R. E. Benner, D. Burke, C. Chan, Jeanine E. Cook, David Donofrio, Simon D. Hammond, Karl S. Hemmert, Suzanne M. Kelly, H. Le, Vitus J. Leung, David R. Resnick, Arun F. Rodrigues, John Shalf
Abstract machine models and proxy architectures for exascale computing. Co-HPC@SC 2014: 25-32 - [c9]Waleed Alkohlani, Jeanine E. Cook, Nafiul Siddique
Insight into Application Performance Using Application-Dependent Characteristics. PMBS@SC 2014: 107-128 - 2013
- [c8]Mustafa Elfituri, Jeanine E. Cook, Jonathan Cook:
Binary instrumentation support for measuring performance in OpenMP programs. SE-CSE@ICSE 2013: 19-23 - 2012
- [c7]Waleed Alkohlani, Jeanine E. Cook:
Towards Performance Predictive Application-Dependent Workload Characterization. SC Companion 2012: 426-436 - 2011
- [j3]Jeanine E. Cook, Jonathan E. Cook, Waleed Alkohlani:
A statistical performance model of the opteron processor. SIGMETRICS Perform. Evaluation Rev. 38(4): 75-80 (2011) - 2010
- [c6]Waleed Alkohlani, Jeanine E. Cook, Ram Srinivasan:
Extending the Monte Carlo Processor Modeling Technique: Statistical Performance Models of the Niagara 2 Processor. ICPP 2010: 363-374
2000 – 2009
- 2007
- [j2]Ram Srinivasan, Eitan Frachtenberg, Olaf M. Lubeck, Scott Pakin, Jeanine E. Cook:
An Idealistic Neuro-PPM Branch Predictor. J. Instr. Level Parallelism 9 (2007) - [c5]Santosh Talli, Ram Srinivasan, Jeanine E. Cook:
Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization. IPCCC 2007: 372-379 - 2006
- [j1]Ram Srinivasan, Jeanine E. Cook, Olaf M. Lubeck:
Performance modeling using Monte Carlo simulation. IEEE Comput. Archit. Lett. 5(1): 38-41 (2006) - [c4]Ram Srinivasan, Jeanine E. Cook, Olaf M. Lubeck:
Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo Approach. SBAC-PAD 2006: 107-116 - 2005
- [c3]Ram Srinivasan, Jeanine E. Cook, Shaun Cooper:
Fast, Accurate Microarchitecture Simulation Using Statistical Phase Detection. ISPASS 2005: 147-156 - [c2]Wiplove Mathur, Jeanine E. Cook:
Improved Estimation for Software Multiplexing of Performance Counters. MASCOTS 2005: 23-34 - 2002
- [c1]Jeanine E. Cook, Richard L. Oliver, Eric E. Johnson:
Toward reducing processor simulation time via dynamic reduction of microarchitecture complexity. SIGMETRICS 2002: 252-253
Coauthor Index
aka: Erik P. DeBenedictis
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