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Satoru Tanoi
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2020 – today
- 2024
- [c4]Shunichi Kubo, Yuji Gendai, Satoshi Miura, Shinsuke Hara, Satoru Tanoi, Akifumi Kasarnatsu, Takeshi Yoshida, Satoshi Tanaka, Shuhei Arnakawa, Minoru Fujishlrna:
A 20Gb/s QPSK Receiver with Mixed-Signal Carrier, Timing, and Data Recovery Using 3-bit ADCs. CICC 2024: 1-2 - 2021
- [c3]Shinsuke Hara, Ruibing Dong, Sangyeop Lee, Kyoya Takano
, Naoya Toshida, Satoru Tanoi, Tatsuo Hagino, Mohamed H. Mubarak, Norihiko Sekine, Issei Watanabe, Akifumi Kasamatsu, Kunio Sakakibara
A 76-Gbit/s 265-GHz CMOS Receiver. A-SSCC 2021: 1-3
2010 – 2019
- 2014
- [j7]Satoru Tanoi, Tetsuo Endoh:
A High Output Resistance 1.2-V VDD Current Mirror with Deep Submicron Vertical MOSFETs. IEICE Trans. Electron. 97-C(5): 423-430 (2014) - 2012
- [j6]Sang-yeop Lee, Hiroyuki Ito, Satoru Tanoi, Noboru Ishihara, Kazuya Masu:
Injection-locked fractional frequency multiplier with automatic reference pulse-selection technique. IEICE Electron. Express 9(21): 1624-1629 (2012) - [j5]Sang-yeop Lee, Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu:
A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65 nm CMOS. IEICE Trans. Electron. 95-C(10): 1589-1597 (2012) - 2011
- [c2]Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu:
A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS. ISOCC 2011: 32-35
2000 – 2009
- 2005
- [j4]Akifumi Kasamatsu, Akio Tanaka
RF-CMOS Implementation of UWB Transceivers and Its Application to Video Transmission. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(9): 2279-2286 (2005)
1990 – 1999
- 1998
- [c1]Satoru Tanoi:
BIST: required for embedded DRAM. ITC 1998: 1149 - 1997
- [j3]Satoru Tanoi, Yasuhiro Tokunaga, Tetsuya Tanabe, Kazuhiko Takahashi, Atsuhiko Okada, Masahiro Itoh, Yoshiki Nagatomo, Yoshio Ohtsuki, Masaru Uesugi:
On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM. IEEE J. Solid State Circuits 32(11): 1735-1742 (1997) - 1996
- [j2]Satoru Tanoi, Tetsuya Tanabe, Kazuhiko Takahashi, Sanpei Miyamoto, Masaru Uesugi:
A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture. IEEE J. Solid State Circuits 31(4): 487-493 (1996) - 1994
- [j1]Satoru Tanoi, Yasuhiro Tanaka, Tetsuya Tanabe, Akio Eta, Toshio Inada, Ryoji Hamazaki, Yoshio Ohtsuki, Masaru Uesugi:
A 32-bank 256-Mb DRAM with cache and TAG. IEEE J. Solid State Circuits 29(11): 1330-1335 (1994)
Coauthor Index
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