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Travis N. Blalock
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2020 – today
- 2023
- [c10]Linsheng Zhang, Divya Duvvuri, Suprio Bhattacharya, Anjana Dissanayake
, Xinjian Liu, Henry L. Bishop, Yaobin Zhang, Travis N. Blalock, Benton H. Calhoun, Steven M. Bowers:
A -102dBm Sensitivity, 2.2μA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR. CICC 2023: 1-2
2010 – 2019
- 2012
- [j7]Stuart N. Wooters, Adam C. Cabe, Zhenyu Qi, Jiajing Wang, Randy W. Mann, Benton H. Calhoun, Mircea R. Stan
Tracking On-Chip Age Using Distributed, Embedded Sensors. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 1974-1985 (2012) - 2010
- [j6]Stuart N. Wooters, Benton H. Calhoun, Travis N. Blalock:
An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 57-II(4): 290-294 (2010) - [c9]Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan
SRAM-based NBTI/PBTI sensor system design. DAC 2010: 849-852
2000 – 2009
- 2009
- [c8]Andrew D. Jurik, Jonathan F. Bolus, Alfred C. Weaver
Mobile health monitoring through biotelemetry. BODYNETS 2009: 12 - [c7]Benton H. Calhoun, Jonathan F. Bolus, Sudhanshu Khanna, Andrew D. Jurik, Alfred C. Weaver
Sub-threshold Operation and Cross-hierarchy Design for Ultra Low Power Wearable Sensors. ISCAS 2009: 1437-1440 - [c6]Steven C. Jocke, Jonathan F. Bolus, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun:
A 2.6 µW sub-threshold mixed-signal ECG SoC. ISLPED 2009: 117-118 - [c5]Adam C. Cabe, Zhenyu Qi, Stuart N. Wooters, Travis N. Blalock, Mircea R. Stan
Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay. ISQED 2009: 1-6 - 2008
- [j5]Michael I. Fuller, Karthik Ranganathan, Shiwei Zhou, Travis N. Blalock, John A. Hossack, William F. Walker:
Experimental System Prototype of a Portable, Low-Cost, C-Scan Ultrasound Imaging Device. IEEE Trans. Biomed. Eng. 55(2): 519-530 (2008) - 2007
- [c4]Brandon L. Dell, Jonathan F. Bolus, Travis N. Blalock:
An automated unique tagging system using CMOS process variation. ACM Great Lakes Symposium on VLSI 2007: 216-218 - 2005
- [c3]Yan Zhang, Travis N. Blalock, Mircea R. Stan
A three-level toggle-avoid bus signaling scheme. ISCAS (2) 2005: 1843-1846 - 2004
- [j4]Girish B. Ratanpal, Ronald D. Williams, Travis N. Blalock:
An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks. IEEE Trans. Dependable Secur. Comput. 1(3): 179-189 (2004) - 2003
- [c2]Michael I. Fuller, James P. Mabry, John A. Hossack, Travis N. Blalock:
40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications. ACM Great Lakes Symposium on VLSI 2003: 182-185 - [c1]Ram Suryanarayan, Anubhav Gupta, Travis N. Blalock:
A slew rate enhancement technique for operational amplifiers based on a tunable active Gm-based capacitance multiplication circuit. ACM Great Lakes Symposium on VLSI 2003: 273-276 - 2001
- [j3]Travis N. Blalock, Neela B. Gaddis, Ken A. Nishimura, Thomas A. Knotts:
True color 1024×768 microdisplay with analog in-pixel pulsewidth modulation and retinal averaging offset correction. IEEE J. Solid State Circuits 36(5): 838-845 (2001)
1990 – 1999
- 1992
- [j2]Travis N. Blalock, Richard C. Jaeger:
A high-speed sensing scheme for 1T dynamic RAMs utilizing the clamped bit-line sense amplifier. IEEE J. Solid State Circuits 27(4): 618-625 (1992) - 1991
- [j1]Travis N. Blalock, Richard C. Jaeger:
A high-speed clamped bit-line current-mode sense amplifier. IEEE J. Solid State Circuits 26(4): 542-548 (1991)
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