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Alessandro Strano
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2010 – 2019
- 2014
- [c17]Alessandro Strano, Alberto Ghiribaldi, Hervé Tatenguem Fankem
, Davide Bertozzi:
A feature-rich NoC switch with cross-feature optimizations for the next generation of reliable and reconfigurable embedded systems. INA-OCMC@HiPEAC 2014: 2:1-2:4 - 2013
- [b1]Alessandro Strano:
Design and Validation of Network-on-Chip Architectures for the Next Generation of Multi-synchronous, Reliable, and Reconfigurable Embedded Systems. University of Ferrara, Italy, 2013 - [j6]Alessandro Strano, Nicola Caselli, Simone Terenzi, Davide Bertozzi:
Optimising pseudo-random built-in self-testing of fully synchronous as well as multisynchronous networks-on-chip. IET Comput. Digit. Tech. 7(2) (2013) - [j5]Alberto Ghiribaldi, Daniele Ludovici, Francisco Triviño, Alessandro Strano, José Flich
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs. ACM Trans. Embed. Comput. Syst. 12(4): 106:1-106:29 (2013) - [j4]Frank Olaf Sem-Jacobsen, Samuel Rodrigo, Tor Skeie, Alessandro Strano, Davide Bertozzi:
An efficient, low-cost routing framework for convex mesh partitions to support virtualization. ACM Trans. Embed. Comput. Syst. 12(4): 107:1-107:24 (2013) - [j3]Frank Olaf Sem-Jacobsen, Samuel Rodrigo, Alessandro Strano, Tor Skeie, Davide Bertozzi, Francisco Gilabert Villamón:
Enabling power efficiency through dynamic rerouting on-chip. ACM Trans. Embed. Comput. Syst. 12(4): 111:1-111:23 (2013) - 2012
- [j2]Milos Krstic
Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience. Int. J. Embed. Real Time Commun. Syst. 3(4): 1-18 (2012) - [c16]Alberto Ghiribaldi, Alessandro Strano, Michele Favalli
Power efficiency of switch architecture extensions for fault tolerant NoC design. IGCC 2012: 1-6 - [c15]Simone Terenzi, Alessandro Strano, Davide Bertozzi:
Optimizing built-in pseudo-random self-testing for network-on-chip switches. INA-OCMC@HiPEAC 2012: 21-24 - [c14]Alessandro Strano, Davide Bertozzi, Federico Angiolini, Leonardo Di G. Gregorio, Frank Olaf Sem-Jacobsen, Vladimir Todorov, José Flich
Quest for the ultimate network-on-chip: the NaNoC project. INA-OCMC@HiPEAC 2012: 43-46 - [c13]Hervé Tatenguem
Ultra-low latency NoC testing via pseudo-random test pattern compaction. ISSoC 2012: 1-6 - [c12]Nicola Caselli, Alessandro Strano, Daniele Ludovici, Davide Bertozzi:
Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels. MCSoC 2012: 159-166 - [c11]Alessandro Strano, Davide Bertozzi, Francisco Triviño, José L. Sánchez
OSR-Lite: Fast and deadlock-free NoC reconfiguration framework. ICSAMOS 2012: 86-95 - 2011
- [j1]Alessandro Strano, Carles Hernández
Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design. Int. J. Embed. Real Time Commun. Syst. 2(4): 1-20 (2011) - [c10]Alessandro Strano, Davide Bertozzi, Arnaud Grasset, Sami Yehia:
Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration. ASAP 2011: 141-148 - [c9]Alessandro Strano, Crispín Gómez Requena, Daniele Ludovici, Michele Favalli, María Engracia Gómez, Davide Bertozzi:
Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture. DATE 2011: 661-666 - [c8]Daniele Ludovici, Alessandro Strano, Georgi Nedeltchev Gaydadjiev
Mesochronous NoC technology for power-efficient GALS MPSoCs. INA-OCMC@HiPEAC 2011: 27-30 - [c7]Milos Krstic
Moonrake chip - GALS demonstrator in 40 nm CMOS technology. SoC 2011: 9-13 - [c6]Hervé Tatenguem
Contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case study. NoCArc@MICRO 2011: 37-42 - 2010
- [c5]Daniele Ludovici, Alessandro Strano, Georgi Nedeltchev Gaydadjiev
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs. DATE 2010: 679-684 - [c4]Alessandro Strano, Carles Hernández
Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip. SoC 2010: 43-48 - [c3]Alessandro Strano, Daniele Ludovici, Davide Bertozzi:
A library of dual-clock FIFOs for cost-effective and flexible MPSoC design. ICSAMOS 2010: 20-27
2000 – 2009
- 2009
- [c2]Daniele Ludovici, Alessandro Strano, Davide Bertozzi:
Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches. NoCArc@MICRO 2009: 31-36 - [c1]Daniele Ludovici, Alessandro Strano, Davide Bertozzi, Luca Benini
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture. NOCS 2009: 244-249
Coauthor Index
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