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Peter Verplaetse
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2000 – 2009
- 2003
- [j3]Joni Dambre
, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout
A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 24-34 (2003) - [c8]Jeroen De Maeyer, Harald Devos, Wim Meeus, Peter Verplaetse, Dirk Stroobandt:
Hardware implementation of an EAN-13 bar code decoder. ASP-DAC 2003: 583-584 - 2002
- [c7]Joni Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout:
Getting more out of Donath's hierarchical model for interconnect prediction. SLIP 2002: 9-16 - 2001
- [j2]Peter Verplaetse, Dirk Stroobandt, Jan M. Van Campenhout
A stochastic model for the interconnection topology of digital circuits. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 938-942 (2001) - [c6]Peter Verplaetse:
Refinements of Rent's Rule Allowing Accurate Interconnect Complexity Modeling. ISQED 2001: 251-252 - [c5]Peter Verplaetse, Joni Dambre, Dirk Stroobandt, Jan Van Campenhout
On partitioning vs. placement rent properties. SLIP 2001: 33-40 - [c4]Joni Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout
On rent's rule for rectangular regions. SLIP 2001: 49-56 - 2000
- [j1]Dirk Stroobandt, Peter Verplaetse, Jan M. Van Campenhout
Generating synthetic benchmark circuits for evaluating CAD tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 1011-1022 (2000) - [c3]Peter Verplaetse, Jan Van Campenhout
On synthetic benchmark generation methods. ISCAS 2000: 213-216
1990 – 1999
- 1999
- [c2]Dirk Stroobandt, Peter Verplaetse, Jan Van Campenhout
Towards synthetic benchmark circuits for evaluating timing-driven CAD tools. ISPD 1999: 60-66 - 1998
- [c1]Jan Van Campenhout, Peter Verplaetse, Henk Neefs:
ESCAPE: environment for the simulation of computer architectures for the purpose of education. WCAE@ISCA 1998: 9
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