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Jean-Marc Gallière
2020 – today
- 2025
- [j7]Gustavo Aguirre
, Freddy Forero
Cost-Effective Analytical Models of Resistive Opens Defects in FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. 33(3): 841-852 (2025) - 2023
- [c27]Geoffrey Chancel, Jean-Marc Gallière, Philippe Maurine:
A better practice for Body Biasing Injection. FDTC 2023: 48-59 - 2022
- [c26]Geoffrey Chancel, Jean Marc Gallière, Philippe Maurine:
Body Biasing Injection: To Thin or Not to Thin the Substrate? COSADE 2022: 125-139 - [c25]Geoffrey Chancel, Jean Marc Gallière, Philippe Maurine:
Body Biasing Injection: Impact of substrate types on the induced disturbancesƒ. FDTC 2022: 50-60 - 2021
- [c24]Gwenael Chaillou, Philippe Maurine, Jean-Marc Gallière, Nadine Azémard:
Iterative Method for Performance Prediction Improvement of Integrated Circuits. DCIS 2021: 1-5 - [c23]Julien Toulemont, Geoffrey Chancel, Jean Marc Gallière, Frédérick Mailly
On the scaling of EMFI probes. FDTC 2021: 67-73 - 2020
- [i1]Julien Toulemont, N. Ouldei-Tebina, Jean Marc Gallière, Pascal Nouet, E. Bourbao, Philippe Maurine:
A Simple Protocol to Compare EMFI Platforms. IACR Cryptol. ePrint Arch. 2020: 1277 (2020)
2010 – 2019
- 2019
- [j6]Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell:
Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies. J. Electron. Test. 35(1): 59-75 (2019) - [c22]Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac:
A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells. LATS 2019: 1-6 - 2018
- [j5]Freddy Forero
Detectability Challenges of Bridge Defects in FinFET Based Logic Cells. J. Electron. Test. 34(2): 123-134 (2018) - [c21]Maxime Cozzi, Jean-Marc Gallière, Philippe Maurine:
Thermal Scans for Detecting Hardware Trojans. COSADE 2018: 117-132 - [c20]Maxime Cozzi, Jean-Marc Gallière, Philippe Maurine:
Exploiting Phase Information in Thermal Scans for Stealthy Trojan Detection. DSD 2018: 573-576 - [c19]Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell:
Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies. LATS 2018: 1-5 - [c18]Rida Kheirallah, Jean-Marc Gallière, Nadine Azémard, Gilles R. Ducharme:
Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy Management. PATMOS 2018: 88-91 - 2017
- [j4]Amit Karel
Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies. J. Electron. Test. 33(4): 515-527 (2017) - [c17]Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell, Keshav Singh:
Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions. ETS 2017: 1-2 - [c16]Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell, Keshav Singh:
Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology. ISVLSI 2017: 320-325 - [c15]Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac:
Analysis of short defects in FinFET based logic cells. LATS 2017: 1-6 - 2016
- [c14]Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell:
Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI - LVT and RVT Configurations. ISVLSI 2016: 164-169 - [c13]Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell:
Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect. LATS 2016: 129-134 - 2014
- [j3]Jean-Marc Gallière, Florence Azaïs, Mariane Comte, Michel Renovell:
Testing for gate oxide short defects using the detectability interval paradigm. it Inf. Technol. 56(4): 173-181 (2014) - 2013
- [c12]Jean-Marc Gallière, Jerome Boch
A toolkit to demystify CMOS Active Pixel Sensors. MSE 2013: 25-27 - 2011
- [c11]Luigi Dilillo, Paolo Rech
Neutron detection in atmospheric environment through static and dynamic SRAM-based test bench. LATW 2011: 1-6 - [c10]Jean-Marc Gallière, Luigi Dilillo:
Versatile march test generator for hands-on memory testing laboratory. MSE 2011: 41-42 - 2010
- [c9]Jean-Marc Gallière, Paolo Rech
A roaming memory test bench for detecting particle induced SEUs. ITC 2010: 810
2000 – 2009
- 2009
- [c8]Jean-Marc Gallière, Jerome Boch
A mixed TCAD/Electrical simulation laboratory to open up the microelectronics teaching. MSE 2009: 37-40 - 2008
- [c7]Jean-Marc Gallière, Philippe Papet, Laurent Latorre:
A 2-D VHDL-AMS Model for Disk-Shape Piezoelectric Transducers. BMAS 2008: 148-152 - 2007
- [c6]Jean-Marc Gallière, Guy Cathébras:
Stream Manager, Easy CAD Tools Switching in Academic Context. MSE 2007: 23-24 - 2005
- [j2]Jean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand:
Delay Testing Viability of Gate Oxide Short Defects. J. Comput. Sci. Technol. 20(2): 195-200 (2005) - [c5]Ilia Polian, Sandip Kundu, Jean-Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. VTS 2005: 343-348 - 2003
- [j1]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short. J. Electron. Test. 19(4): 377-386 (2003) - [c4]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Delay Testing of MOS Transistor with Gate Oxide Short. Asian Test Symposium 2003: 168-173 - 2002
- [c3]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Modeling gate oxide short defects in CMOS minimum transistors. ETW 2002: 15-20 - 2001
- [c2]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Serge Bernard, Yves Bertrand:
Boolean and current detection of MOS transistor with gate oxide short. ITC 2001: 1039-1048 - [c1]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Electrical Analysis of Gate Oxide Short in MOS Technologies. LATW 2001: 266-272
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last updated on 2025-04-09 21:29 CEST by the dblp team
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