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Eduardo J. Peralías
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- affiliation: University of Seville, Spain
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2020 – today
- 2023
- [j17]Carlos Manuel Domínguez-Matas
, Antonio J. Ginés
Behavioral Model for High-Speed SAR ADCs With On-Chip References. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 1918-1930 (2023) - [c48]Gildas Léger, Antonio J. Ginés, Eduardo J. Peralías, Valentin Gutierrez, C. Dominguez, Maria Angeles Jalón, L. Carranza:
A Single-Event Latchup setup for high-precision AMS circuits. ETS 2023: 1-6 - 2021
- [j16]Antonio J. Ginés
Digital Non-Linearity Calibration for ADCs With Redundancy Using a New LUT Approach. IEEE Trans. Circuits Syst. I Regul. Pap. 68(8): 3197-3210 (2021) - 2020
- [j15]Rafaella Fiorelli
Normalized Nonlinear Semiempirical MOST Model Used in Monolithic RF Class A-to-C PAs. Circuits Syst. Signal Process. 39(6): 2796-2821 (2020) - [c47]Antonio Lopez-Angulo, Antonio J. Ginés, Eduardo J. Peralías:
Calibration of Capacitor Mismatch and Static Comparator Offset in SAR ADC with Digital Redundancy. ISCAS 2020: 1-5 - [c46]J. A. Serrano, Antonio J. Ginés, Eduardo J. Peralías:
Fast Simulation of Non-Linear Circuits using Semi-Analytical Solutions Based on the Matrix Exponential. ISCAS 2020: 1-5 - [c45]Antonio Lopez-Angulo, Antonio J. Ginés, Eduardo J. Peralías:
Digital calibration of capacitor mismatch and comparison offset in Split-CDAC SAR ADCs with redundancy. NEWCAS 2020: 130-133 - [c44]Antonio J. Ginés, Gildas Léger, Eduardo J. Peralías:
Non-Linear Calibration of Pipeline ADCs using a Histogram-Based Estimation of the Redundant INL. NEWCAS 2020: 142-145
2010 – 2019
- 2019
- [j14]Antonio Jose Ginés
Fast adaptive comparator offset calibration in pipeline ADC with self-repairing thermometer to binary encoder. Int. J. Circuit Theory Appl. 47(3): 333-349 (2019) - [c43]Antonio Lopez-Angulo, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda:
Mismatch and Offset Calibration in Redundant SAR ADC. DCIS 2019: 1-5 - 2018
- [c42]Antonio Lopez-Angulo
Redundant SAR ADCs with Split-capacitor DAC. ICECS 2018: 801-804 - [c41]Antonio J. Ginés, Antonio Lopez-Angulo
Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach. ISCAS 2018: 1-5 - 2017
- [j13]Antonio J. Ginés
Black-Box Calibration for ADCs With Hard Nonlinear Errors Using a Novel INL-Based Additive Code: A Pipeline ADC Case Study. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(7): 1718-1729 (2017) - [j12]Antonio J. Ginés
Fast Background Calibration of Sampling Timing Skew in SHA-Less Pipeline ADCs. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2966-2970 (2017) - [c40]Manuel J. Barragán, Gildas Léger
On the limits of machine learning-based test: A calibrated mixed-signal system case study. DATE 2017: 79-84 - 2016
- [j11]Rafaella Fiorelli
Semi-empirical RF MOST model for CMOS 65 nm technologies: Theory, extraction method and validation. Integr. 52: 228-236 (2016) - [c39]Antonio J. Ginés
Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator. ETS 2016: 1-6 - 2015
- [j10]Antonio Jose Ginés
Background Digital Calibration of Comparator Offsets in Pipeline ADCs. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1345-1349 (2015) - [c38]Juan Núñez
An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs. LASCAS 2015: 1-4 - 2014
- [c37]Eduardo J. Peralías
INL systematic reduced-test technique for Pipeline ADCs. ETS 2014: 1-6 - [c36]Antonio J. Ginés
Closed-loop simulation method for evaluation of static offset in discrete-time comparators. ICECS 2014: 538-541 - 2012
- [c35]Antonio Jose Ginés
Self-biased input common-mode generation for improving dynamic range and yield in inverter-based filters. ICECS 2012: 256-259 - [c34]Ricardo Doldán, Antonio J. Ginés
Analysis of steady-state common-mode response in differential LC-VCOs. ISCAS 2012: 2031-2034 - 2011
- [j9]Antonio J. Ginés
Blind Adaptive Estimation of Integral Nonlinear Errors in ADCs Using Arbitrary Input Stimulus. IEEE Trans. Instrum. Meas. 60(2): 452-461 (2011) - [c33]Rafaella Fiorelli
2.4-GHz single-ended input low-power low-voltage active front-end for ZigBee applications in 90 nm CMOS. ECCTD 2011: 829-832 - [c32]Alberto Villegas, Diego Vázquez, Eduardo J. Peralías
A 3.6mW @ 1.2V high linear 8th-order CMOS complex filter for IEEE 802.15.4 standard. ESSCIRC 2011: 99-102 - 2010
- [j8]Maria Angeles Jalón, Eduardo J. Peralías
ADC Non-Linearity Low-Cost Test Through a Simplified Double-Histogram Method. J. Electron. Test. 26(1): 47-58 (2010) - [j7]Gildas Léger
On Chopper Effects in Discrete-Time SigmaDelta Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(9): 2438-2449 (2010) - [c31]Antonio J. Ginés
Power optimization of CMOS programmable gain amplifiers with high dynamic range and common-mode feed-forward circuit. ICECS 2010: 45-48 - [c30]Rafaella Fiorelli
A fully differential monolithic 2.4GHZ PA for IEEE 802.15.4 based on efficiency design flow. ICECS 2010: 603-606 - [c29]Antonio J. Ginés
On-chip biased voltage-controlled oscillator with temperature compensation of the oscillation amplitude for robust I/Q generation. ISCAS 2010: 1979-1982
2000 – 2009
- 2009
- [c28]Antonio J. Ginés
On-line estimation of the integral non-linear errors in analogue-to-digital converters without histogram evaluation. ECCTD 2009: 97-100 - [c27]Antonio J. Ginés
A survey on digital background calibration of ADCs. ECCTD 2009: 101-104 - [c26]Rafaella Fiorelli
Phase noise - consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologies. SBCCI 2009 - 2008
- [j6]Eduardo J. Peralías
Simple Evaluation of the Nonlinearity Signature of an ADC Using a Spectral Approach. VLSI Design 2008: 657207:1-657207:8 (2008) - [c25]Ricardo Doldán Lorenzo, Antonio Jose Ginés Arteaga, Adoración Rueda
A 5GHz wide tuning range LC-VCO in sub-micrometer CMOS technology. APCCAS 2008: 558-561 - [c24]Antonio Jose Ginés
A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications. APCCAS 2008: 1252-1255 - [c23]Rafaella Fiorelli
A 2.4GHz LNA in a 90-nm CMOS technology designed with ACM model. SBCCI 2008: 70-75 - 2007
- [c22]Antonio J. Ginés, Eduardo J. Peralías
Improved Background Algorithms for Pipeline ADC Full Calibration. ISCAS 2007: 3383-3386 - [c21]Antonio J. Ginés
Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS. SBCCI 2007: 21-26 - 2006
- [c20]Antonio J. Ginés, Eduardo J. Peralías
Statistical analysis of a background correlation-based technique for full calibration of pipeline ADCs. ISCAS 2006 - 2005
- [c19]Guillermo Zatorre-Navarro, Eduardo J. Peralías
Digital self-tuning technique for continuous-time filters. ICECS 2005: 1-4 - [c18]Antonio J. Ginés
Full calibration digital techniques for pipeline ADCs. ISCAS (3) 2005: 1976-1979 - 2004
- [j5]Gildas Léger
Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(1): 140-150 (2004) - [c17]Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda:
Digital Background Gain Error Correction in Pipeline ADCs. DATE 2004: 82-87 - 2003
- [c16]Antonio J. Ginés
Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages. SBCCI 2003: 317-322 - 2002
- [j4]Gloria Huertas
Practical Oscillation-Based Test of Integrated Filters. IEEE Des. Test Comput. 19(6): 64-72 (2002) - [j3]Gloria Huertas
Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell. IEEE Des. Test Comput. 19(6): 73-82 (2002) - [c15]Antonio J. Ginés
A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects. DATE 2002: 310-314 - 2001
- [j2]Eduardo J. Peralías
New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters. J. Electron. Test. 17(5): 373-383 (2001) - [c14]Natividad Martínez Madrid
Analog/mixed-signal IP modeling for design reuse. DATE 2001: 766-767 - [c13]Eduardo J. Peralías, Adoración Rueda, José L. Huertas:
Structural testing of pipelined analog to digital converters. ISCAS (1) 2001: 436-439 - [c12]Eduardo J. Peralías, Gloria Huertas, Adoración Rueda, José L. Huertas:
Self-Testable Pipelined ADC with Low Hardware Overhead. VTS 2001: 272-278 - 2000
- [c11]Gloria Huertas, Diego Vázquez, Eduardo J. Peralías
Testing mixed-signal cores: practical oscillation-based test in an analog macrocell. Asian Test Symposium 2000: 31-38 - [c10]Eduardo J. Peralías
A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters. DATE 2000: 534-538 - [c9]Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas:
VHDL-based behavioural description of pipeline ADCs. ISCAS 2000: 681-684 - [c8]Eduardo J. Peralías, Adoración Rueda, José L. Huertas:
Alternative DFT Strategies for High-Speed Pipelined Data Converters. LATW 2000: 123-127 - [c7]Raúl Jiménez, Antonio J. Acosta, Eduardo J. Peralías, Adoración Rueda:
An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits. PATMOS 2000: 295-305
1990 – 1999
- 1998
- [j1]Diego Vázquez, Adoración Rueda
A high-Q bandpass fully differential SC filter with enhanced testability. IEEE J. Solid State Circuits 33(7): 976-986 (1998) - [c6]Juan A. Prieto, Adoración Rueda, Ian Andrew Grout, Eduardo J. Peralías
An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits. DATE 1998: 905-909 - [c5]Eduardo J. Peralías, Adoración Rueda, José L. Huertas:
CMOS pipelined A/D converters with concurrent error detection capability. ICECS 1998: 437-440 - [c4]Eduardo J. Peralías, Adoración Rueda, Juan A. Prieto, José L. Huertas:
DfT and on-line test of high-performance data converters: a practical case. ITC 1998: 534-540 - 1997
- [c3]Salvador Mir, Adoración Rueda, Thomas Olbrich, Eduardo J. Peralías, José Luis Huertas:
SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems. DAC 1997: 281-286 - [c2]Eduardo J. Peralías, Adoración Rueda, José L. Huertas:
A DFT Technique for Analog-to-Digital Converters with digital correction. VTS 1997: 302-307 - 1995
- [c1]Eduardo J. Peralías, Adoración Rueda, José Luis Huertas:
Statistical behavioral modeling and characterization of A/D converters. ICCAD 1995: 562-566
Coauthor Index
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