default search action
Yen-Tai Lai
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2010 – 2019
- 2016
- [j16]Chao-Feng Tseng, Yen-Tai Lai:
Fast coding unit decision and mode selection for intra-frame coding in high-efficiency video coding. IET Image Process. 10(3): 215-221 (2016) - [j15]Chao-Feng Tseng, Yen-Tai Lai:
A High-Throughput JPEG XR Encoder. J. Signal Process. Syst. 85(2): 249-261 (2016) - 2014
- [j14]Hung-Yi Lin, Yen-Tai Lai:
Design of a 1-GSample/s 9-b double sampling track-and-hold amplifier in BiCMOS technology. Int. J. Circuit Theory Appl. 42(5): 511-528 (2014) - 2013
- [j13]Hung-Yi Lin, Yen-Tai Lai:
Design of Low Power Two-phase CMOS Buffer for Large capacitive loading Applications. J. Circuits Syst. Comput. 22(2) (2013) - [j12]Chi-Chou Kao, Yen-Tai Lai:
Improved Time-Multiplexed FPGA Architecture and Algorithm for Minimizing Communication Cost Designs. J. Circuits Syst. Comput. 22(5) (2013) - [j11]Tzu-Chiang Tai, Yen-Tai Lai:
Power minimization for dynamically reconfigurable FPGA partitioning. ACM Trans. Embed. Comput. Syst. 12(1s): 52:1-52:22 (2013) - 2012
- [c15]Chi-Chou Kao, Yen-Tai Lai, Chao-Feng Tseng:
Laplacian-based H.264 intra-prediction mode decision. CHINACOM 2012: 638-641 - 2011
- [j10]Yen-Tai Lai, Hung-Yi Lin:
A low distortion CMOS continuous-time common-mode feedback circuit. Int. J. Circuit Theory Appl. 39(12): 1231-1246 (2011) - [j9]Tzu-Chiang Tai, Yen-Tai Lai:
A Performance-Oriented Algorithm with Consideration on Communication Cost for Dynamically Reconfigurable FPGA Partitioning. ACM Trans. Reconfigurable Technol. Syst. 4(2): 16:1-16:18 (2011) - 2010
- [j8]Chi-Chou Kao, Yen-Tai Lai, Chia-Hui Lin:
An efficient reflection invariance region-based image retrieval framework. Int. J. Imaging Syst. Technol. 20(2): 155-161 (2010) - [j7]Yen-Tai Lai, Chi-Chou Kao, Tzu-Chiang Tai, Wen-Chun Yeh:
A Performance-Driven Rotational Invariant Image Retrieval System. J. Inf. Sci. Eng. 26(6): 2009-2022 (2010)
2000 – 2009
- 2009
- [c14]Yen-Tai Lai, Chia-Nan Yeh, Chi-Chou Kao:
A Novel Digital Pixel Sensor System. ISCAS 2009: 2297-2300 - 2008
- [c13]Chia-Nan Yeh, Yen-Tai Lai:
A novel flash analog-to-digital converter. ISCAS 2008: 2250-2253 - 2006
- [c12]Chia-Nan Yeh, Yen-Tai Lai:
Low power readout control circuit for high resolution CMOS image sensor. ISCAS 2006 - 2005
- [j6]Chi-Chou Kao, Yen-Tai Lai:
An efficient algorithm for finding the minimal-area FPGA technology mapping. ACM Trans. Design Autom. Electr. Syst. 10(1): 168-186 (2005) - [c11]Yen-Tai Lai, Hsin-Ya Lai, Chia-Nan Yeh:
Placement for the reconfigurable datapath architecture. ISCAS (2) 2005: 1875-1878 - [c10]Yen-Tai Lai, Yung-Chuan Jiang, Hong-Ming Chu:
BDD decomposition for mixed CMOS/PTL logic circuit synthesis. ISCAS (6) 2005: 5649-5652 - 2004
- [c9]Chi-Chou Kao, Yen-Tai Lai:
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction. ASP-DAC 2004: 719-724 - 2003
- [c8]Chi-Chou Kao, Yen-Tai Lai:
A technology mapping algorithm for heterogeneous FPGAs. ASP-DAC 2003: 213-216 - 2002
- [c7]Yen-Tai Lai, Stephen S.-T. Yau, Ping-Hua Chen:
Design of the ordinary differential equation solver in the Yau filtering system. ACC 2002: 5144-5149 - 2001
- [j5]Lih-Yang Wang, Yen-Tai Lai:
Graph-theory-based simplex algorithm for VLSI layout spacingproblems with multiple variable constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(8): 967-979 (2001)
1990 – 1999
- 1999
- [c6]Yen-Tai Lai, Chi-Chou Kao, Wu-Chien Shieh:
A quadratic programming method for interconnection crosstalk minimization. ISCAS (6) 1999: 270-273 - [c5]Chi-Chou Kao, Yen-Tai Lai:
A routability and performance driven technology mapping algorithm for LUT based FPGA designs. ISCAS (1) 1999: 474-477 - 1997
- [j4]Yen-Tai Lai, Ping-Tsung Wang:
Hierarchical interconnection structures for field programmable gate arrays. IEEE Trans. Very Large Scale Integr. Syst. 5(2): 186-196 (1997) - 1995
- [j3]Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Tin-Chung Chang:
Performance-directed compaction for VLSI symbolic layouts. Comput. Aided Des. 27(1): 65-74 (1995) - 1994
- [c4]Ping-Tsung Wang, Kun-Nen Chen, Yen-Tai Lai:
A High Performance FPGA with Hierarchical Interconnection Structure. ISCAS 1994: 239-242 - 1993
- [c3]Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Ting-Chung Chang:
A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical paths. ICCAD 1993: 703-708 - [c2]Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Tin-Chung Chang:
Layout Compaction with Minimzed Delay Bound on Timing Critical Paths. ISCAS 1993: 1849-1852 - 1990
- [j2]Yen-Tai Lai, Sany M. Leinwand:
A Theory of Rectangular Dual Graphs. Algorithmica 5(4): 467-483 (1990)
1980 – 1989
- 1988
- [j1]Yen-Tai Lai, Sany M. Leinwand:
Algorithms for floorplan design via rectangular dualization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(12): 1278-1289 (1988) - 1984
- [c1]Sany M. Leinwand, Yen-Tai Lai:
An algorithm for building rectangular floor-plans. DAC 1984: 663-664
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-04-25 05:55 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: