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Jianfeng Zhu 0001
Person information
- affiliation: Tsinghua University, Beijing, China
Other persons with the same name
- Jianfeng Zhu — disambiguation page
- Jianfeng Zhu 0002 — Xiamen University, Xiamen, China
- Jianfeng Zhu 0003
— University of Technology Sydney, Ultimo, NSW, Australia
- Jianfeng Zhu 0004 — Science and Technology on Communication Information Security Control Laboratory, Jiaxing, Zhejiang, China
- Jianfeng Zhu 0005 — Huawei
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2020 – today
- 2026
- [j25]Jinyi Chen
EDWAC: A Deadlock-Free Scheme for Compiling Whole Programs Onto Dynamically Reconfigurable Dataflow Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 45(1): 204-217 (2026) - [c17]Yi Huang, Hao Kong
SharpSAT: A Heuristic-Learning-Based SAT Accelerator Achieving 0.8μs/16.1μs Solution Time in SAT/UNSAT Cases. ISSCC 2026: 184-186 - 2025
- [j24]Anlin Xu, Chenchen Deng, Jianfeng Zhu, Yao Wang, Shaojun Wei, Leibo Liu
Software-defined process-near-memory architecture using 3D hybrid bonding integration. Sci. China Inf. Sci. 68(1) (2025) - [j23]Jianfeng Zhu
A 28-nm Software-Defined Accelerator Chip With Circuit-Pipeline Scaling and Intrinsic Physical Unclonable Function Enabling Secure Configuration. IEEE J. Solid State Circuits 60(8): 3053-3065 (2025) - [j22]Yichi Zhang
A 28-nm 239-bp/μJ Agile Pangenome Analysis Accelerator for Multi-Scheme Read Mapping. IEEE J. Solid State Circuits 60(10): 3779-3789 (2025) - [j21]Xiangyu Kong
Raccoon: Lightweight Support for Comprehensive Control Flows in Reconfigurable Spatial Architectures. IEEE Trans. Parallel Distributed Syst. 36(6): 1294-1310 (2025) - [j20]Weiyi Sun
SSS-DIMM: Removing Redundant Data Movement in Trusted DIMM-Based Near-Memory-Processing Kernel Offloading via Secure Space Sharing. IEEE Trans. Parallel Distributed Syst. 36(8): 1810-1827 (2025) - [j19]Menghao Guo
Exploiting Fine-Grained Task-Level Parallelism for Variant Calling Acceleration. IEEE Trans. Parallel Distributed Syst. 36(11): 2169-2181 (2025) - [c16]Iris Ying Chou, Hao Kong
Chameleon-SAT: An Adaptive Boolean Satisfiability Accelerator Using Mixed-Signal In-Memory Computing for Versatile SAT Problems. DAC 2025: 1-7 - [c15]Yi Huang, Xinsheng Gong, Xiangyu Kong, Dibei Chen, Jianfeng Zhu, Wenping Zhu, Liangwei Li
EFFACT: A Highly Efficient Full-Stack FHE Acceleration Platform. HPCA 2025: 1143-1157 - [c14]Weiyi Sun, Mingyu Gao, Zhaoshi Li, Aoyang Zhang, Iris Ying Chou, Jianfeng Zhu, Shaojun Wei, Leibo Liu
Lincoln: Real-Time 50~100B LLM Inference on Consumer Devices with LPDDR-Interfaced, Compute-Enabled Flash Memory. HPCA 2025: 1734-1750 - [c13]Meng Han
PointISA: ISA-Extensions for Efficient Point Cloud Analytics via Architecture and Algorithm Co-Design. MICRO 2025: 1867-1881 - [i3]Yi Huang, Xinsheng Gong, Xiangyu Kong, Dibei Chen, Jianfeng Zhu, Wenping Zhu, Liangwei Li, Mingyu Gao, Shaojun Wei, Aoyang Zhang, Leibo Liu
EFFACT: A Highly Efficient Full-Stack FHE Acceleration Platform. CoRR abs/2504.15817 (2025) - [i2]Buqing Xu, Jianfeng Zhu, Yichi Zhang, Qinyi Cai, Guanhua Li, Shaojun Wei, Leibo Liu
CAPSim: A Fast CPU Performance Simulator Using Attention-based Predictor. CoRR abs/2510.10484 (2025) - [i1]Xianshuai Shi, Jianfeng Zhu, Leibo Liu
Gate-level boolean evolutionary geometric attention neural networks. CoRR abs/2511.17550 (2025) - 2024
- [j18]Chenchen Deng, Tianzhu Xiong, Zhaoshi Li, Zhiwei Liu, Yao Wang, Jianfeng Zhu, Jun Yang, Shaojun Wei, Leibo Liu
CATCAM: a 28 nm constant-time alteration TCAM enabling less than 50 ns update latency. Sci. China Inf. Sci. 67(4) (2024) - [j17]Xiangren Chen, Bohan Yang, Jianfeng Zhu, Jun Liu, Shuying Yin, Guang Yang, Min Zhu, Shaojun Wei, Leibo Liu
UpWB: An Uncoupled Architecture Design for White-box Cryptography Using Vectorized Montgomery Multiplication. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024(2): 677-713 (2024) - [j16]Gang Zeng
A High-Performance Genomic Accelerator for Accurate Sequence-to-Graph Alignment Using Dynamic Programming Algorithm. IEEE Trans. Parallel Distributed Syst. 35(2): 237-249 (2024) - [c12]Yichi Zhang
Harp: Leveraging Quasi-Sequential Characteristics to Accelerate Sequence-to-Graph Mapping of Long Reads. ASPLOS (3) 2024: 512-527 - 2023
- [j15]Xiangyu Kong
M2STaR: A Multimode Spatio-Temporal Redundancy Design for Fault-Tolerant Coarse-Grained Reconfigurable Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2938-2951 (2023) - [j14]Meng Han
QuickFPS: Architecture and Algorithm Co-Design for Farthest Point Sampling in Large-Scale Point Clouds. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4011-4024 (2023) - [j13]Longlong Chen
GEM: Ultra-Efficient Near-Memory Reconfigurable Acceleration for Read Mapping by Dividing and Predictive Scattering. IEEE Trans. Parallel Distributed Syst. 34(12): 3059-3072 (2023) - [c11]Dibei Chen
Orinoco: Ordered Issue and Unordered Commit with Non-Collapsible Queues. ISCA 2023: 11:1-11:14 - [c10]Xiangyu Kong
MapZero: Mapping for Coarse-grained Reconfigurable Architectures with Reinforcement Learning and Monte-Carlo Tree Search. ISCA 2023: 46:1-46:14 - [c9]Yibo Wu
Shogun: A Task Scheduling Framework for Graph Mining Accelerators. ISCA 2023: 51:1-51:15 - [c8]Yi Huang
CASA: An Energy-Efficient and High-Speed CAM-based SMEM Seeding Accelerator for Genome Alignment. MICRO 2023: 1423-1436 - 2022
- [b1]Shaojun Wei, Leibo Liu
Software Defined Chips - Volume I, 2. Springer 2022, ISBN 978-981-19-6993-5, pp. 1-311 - [j12]Chenchen Deng, Min Zhu, Jinjiang Yang, Youyu Wu, Jiaji He, Bohan Yang
An energy-efficient dynamically reconfigurable cryptographic engine with improved power/EM-side-channel-attack resistance. Sci. China Inf. Sci. 65(4) (2022) - [j11]Baofen Yuan
Dynamic-II Pipeline: Compiling Loops With Irregular Branches on Static-Scheduling CGRA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 2929-2942 (2022) - [c7]Yibo Wu, Liang Wang, Xiaohang Wang, Jie Han, Jianfeng Zhu, Honglan Jiang, Shouyi Yin, Shaojun Wei, Leibo Liu
Upward Packet Popup for Deadlock Freedom in Modular Chiplet-Based Systems. HPCA 2022: 986-1000 - [c6]Xingchen Man
CaSMap: agile mapper for reconfigurable spatial architectures by automatically clustering intermediate representations and scattering mapping process. ISCA 2022: 259-273 - 2021
- [j10]Jianfeng Zhu, Ao Luo, Guanhua Li, Bowei Zhang, Yong Wang, Gang Shan, Yi Li, Jianfeng Pan, Chenchen Deng, Shouyi Yin, Shaojun Wei, Leibo Liu:
Jintide: Utilizing Low-Cost Reconfigurable External Monitors to Substantially Enhance Hardware Security of Large-Scale CPU Clusters. IEEE J. Solid State Circuits 56(8): 2585-2601 (2021) - [j9]Longlong Chen
An Elastic Task Scheduling Scheme on Coarse-Grained Reconfigurable Architectures. IEEE Trans. Parallel Distributed Syst. 32(12): 3066-3080 (2021) - 2020
- [j8]Leibo Liu
A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications. ACM Comput. Surv. 52(6): 118:1-118:39 (2020) - [j7]Leibo Liu
Pattern-Based Dynamic Compilation System for CGRAs With Online Configuration Transformation. IEEE Trans. Parallel Distributed Syst. 31(12): 2981-2994 (2020)
2010 – 2019
- 2019
- [c5]Xingchen Man
A General Pattern-Based Dynamic Compilation Framework for Coarse-Grained Reconfigurable Architectures. DAC 2019: 195 - [c4]Leibo Liu
Jintide®: A Hardware Security Enhanced Server CPU with Xeon® Cores under Runtime Surveillance by an In-Package Dynamically Reconfigurable Processor. Hot Chips Symposium 2019: 1-25 - 2016
- [j6]Leibo Liu
TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions. IEEE Trans. Parallel Distributed Syst. 27(7): 2143-2154 (2016) - 2015
- [j5]Jianfeng Zhu, Leibo Liu
A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1700-1709 (2015) - [c3]Junbin Wang, Leibo Liu
Acceleration of control flows on reconfigurable architecture with a composite method. DAC 2015: 45:1-45:6 - [c2]Junbin Wang, Leibo Liu
A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only). FPGA 2015: 270 - 2014
- [j4]Jianfeng Zhu, Liyang Pan, Yaru Yan, Dong Wu, Hu He:
A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2629-2634 (2014) - 2013
- [j3]Jianfeng Zhu, Leibo Liu
Low-Power Reconfigurable Processor Utilizing Variable Dual VDD. IEEE Trans. Circuits Syst. II Express Briefs 60-II(4): 217-221 (2013) - 2011
- [j2]Jianfeng Zhu, Hu He, Dong Wu, Liyang Pan:
A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect. J. Electron. Test. 27(5): 647-655 (2011) - [j1]Jianfeng Zhu, Hu He, Dong Wu, Liyang Pan:
Erratum to: A Cost-Efficient Self-Configurable BIST Technique for Testing Multiplexer-Based FPGA Interconnect. J. Electron. Test. 27(5): 679 (2011) - [c1]Jianfeng Zhu, Dong Wu, Yaru Yan, Xiao Yu, Hu He, Liyang Pan:
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only). FPGA 2011: 281
Coauthor Index
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