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Kaijie Wu 0001
Person information
- affiliation: Chongqing University, College of Computer Science, China
- affiliation: Ministry of Education, Key Laboratory of Cyber Physical Society Credible Service Computing, Chongqing, China
Other persons with the same name
- Kaijie Wu 0002
— Shanghai Jiao Tong University, Department of Automation, China
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2020 – today
- 2022
- [j39]Xiaotong Cui
Toward Building and Optimizing Trustworthy Systems Using Untrusted Components: A Graph-Theoretic Perspective. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1386-1399 (2022) - 2020
- [j38]Xiaotong Cui
On the Difficulty of Inserting Trojans in Reversible Computing Architectures. IEEE Trans. Emerg. Top. Comput. 8(4): 960-972 (2020)
2010 – 2019
- 2019
- [j37]Xiaotong Cui
Split Manufacturing-Based Register Transfer-Level Obfuscation. ACM J. Emerg. Technol. Comput. Syst. 15(1): 11:1-11:22 (2019) - [j36]Yejia Di
Minimizing Retention Induced Refresh Through Exploiting Process Variation of Flash Memory. IEEE Trans. Computers 68(1): 83-98 (2019) - [j35]Christian Pilato
TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 798-808 (2019) - 2018
- [j34]Christian Pilato
Securing Hardware Accelerators: A New Challenge for High-Level Synthesis. IEEE Embed. Syst. Lett. 10(3): 77-80 (2018) - [j33]Xiaotong Cui
Hardware Trojan Detection Using the Order of Path Delay. ACM J. Emerg. Technol. Comput. Syst. 14(3): 33:1-33:23 (2018) - [j32]Congming Gao, Liang Shi
Exploiting Parallelism for Access Conflict Minimization in Flash-Based Solid State Drives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(1): 168-181 (2018) - [j31]Minhui Zou, Xiaotong Cui
Potential Trigger Detection for Hardware Trojans. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1384-1395 (2018) - [j30]Congming Gao, Liang Shi, Yejia Di, Qiao Li
Exploiting Chip Idleness for Minimizing Garbage Collection - Induced Chip Access Conflict on SSDs. ACM Trans. Design Autom. Electr. Syst. 23(2): 15:1-15:29 (2018) - [c41]Xiaotong Cui
Hardware Trojan detection using path delay order encoding with process variation tolerance. ETS 2018: 1-2 - [c40]Yejia Di, Liang Shi, Congming Gao, Qiao Li
Loss is Gain: Shortening Data for Lifetime Improvement on Low-Cost ECC Enabled Consumer-Level Flash Memory. ACM Great Lakes Symposium on VLSI 2018: 225-230 - [c39]Samah Mohamed Saeed, Xiaotong Cui
IC/IP piracy assessment of reversible logic. ICCAD 2018: 5 - 2017
- [j29]Zhilong Sun, Edwin H.-M. Sha, Qingfeng Zhuge, Xianzhang Chen, Kaijie Wu:
面向内存文件系统的数据一致性更新机制研究 (Research on Data Consistency for In-memory File Systems). 计算机科学 44(2): 222-227 (2017) - [j28]Xiaotong Cui
Towards trustworthy storage using SSDs with proprietary FTL. Microprocess. Microsystems 55: 82-90 (2017) - [j27]Edwin Hsing-Mean Sha, Congming Gao, Liang Shi
Asymmetric Error Rates of Cell States Exploration for Performance Improvement on Flash Memory Based Storage Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(8): 1340-1352 (2017) - [c38]Qiao Li
A PV aware data placement scheme for read performance improvement on LDPC based flash memory: work-in-progress. CODES+ISSS 2017: 3:1-3:2 - [i4]Samah Mohamed Saeed, Xiaotong Cui, Robert Wille, Alwin Zulehner, Kaijie Wu, Rolf Drechsler, Ramesh Karri:
Towards Reverse Engineering Reversible Logic. CoRR abs/1704.08397 (2017) - [i3]Xiaotong Cui, Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Rolf Drechsler, Kaijie Wu, Ramesh Karri:
On the Difficulty of Inserting Trojans in Reversible Computing Architectures. CoRR abs/1705.00767 (2017) - 2016
- [j26]Xiaotong Cui
Worst-Case Finish Time Analysis for DAG-Based Applications in the Presence of Transient Faults. J. Comput. Sci. Technol. 31(2): 267-283 (2016) - [j25]Liang Shi, Kaijie Wu
Retention Trimming for Lifetime Improvement of Flash Memory Storage Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(1): 58-71 (2016) - [j24]Liang Shi, Yejia Di, Mengying Zhao, Chun Jason Xue
Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 334-337 (2016) - [j23]Kaijie Wu, Zili Shao
Guest Editorial: Real-Time and Embedded Systems. J. Signal Process. Syst. 84(1): 1-2 (2016) - [c37]Yejia Di, Liang Shi, Kaijie Wu, Chun Jason Xue:
Exploiting process variation for retention induced refresh minimization on flash memory. DATE 2016: 391-396 - [c36]Xiaotong Cui, Kaijie Wu, Siddharth Garg, Ramesh Karri
Can flexible, domain specific programmable logic prevent IP theft? DFT 2016: 153-157 - [c35]Qiao Li, Liang Shi, Chun Jason Xue, Kaijie Wu, Cheng Ji, Qingfeng Zhuge, Edwin Hsing-Mean Sha:
Access Characteristic Guided Read and Write Cost Regulation for Performance Improvement on Flash Memory. FAST 2016: 125-132 - [c34]Yejia Di, Liang Shi, Congming Gao, Kaijie Wu, Chun Jason Xue, Edwin Hsing-Mean Sha:
Minimizing cell-to-cell interference by exploiting differential bit impact characteristics of scaled MLC NAND flash memories. NVMSA 2016: 1-6 - 2015
- [j22]Junlong Zhou, Jianming Yan, Tongquan Wei, Kaijie Wu, Xiaodao Chen, Shiyan Hu:
Sharp Corner/Edge Recognition in Domestic Environments Using RGB-D Camera Systems. IEEE Trans. Circuits Syst. II Express Briefs 62-II(10): 987-991 (2015) - [c33]Qiao Li, Liang Shi, Congming Gao, Kaijie Wu, Chun Jason Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha:
Maximizing IO performance via conflict reduction for flash memory storage systems. DATE 2015: 904-907 - [c32]Xiaotong Cui, Minhui Zou, Liang Shi, Kaijie Wu:
Towards trustable storage using SSDs with proprietary FTL. DATE 2015: 1213-1216 - [c31]Xiaohao Lin, Weichen Liu
Realistic Task Parallelization of the H.264 Decoding Algorithm for Multiprocessors. HPCC/CSS/ICESS 2015: 871-874 - [c30]Jie Dai, Weichen Liu
User Experience Enhanced Task Scheduling and Processor Frequency Scaling for Energy-Sensitive Mobile Devices. HPCC/CSS/ICESS 2015: 941-944 - 2014
- [j21]Jun Zhang, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Juan Yi, Kaijie Wu:
Efficient fault-tolerant scheduling on multiprocessor systems via replication and deallocation. Int. J. Embed. Syst. 6(2/3): 216-224 (2014) - [j20]Minhui Zou, Kun Ma, Kaijie Wu, Edwin Hsing-Mean Sha:
Scan-Based Attack on Stream Ciphers: A Case Study on eSTREAM Finalists. J. Comput. Sci. Technol. 29(4): 646-655 (2014) - [j19]Kun Ma, Kaijie Wu:
Error Detection and Recovery for ECC: A New Approach Against Side-Channel Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 627-637 (2014) - [j18]Yu Liu, Kaijie Wu:
Fault-Duration And-Location Aware CED Technique With Runtime Adaptability. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 507-515 (2014) - [c29]Xiaotong Cui, Jun Zhang, Kaijie Wu, Edwin Hsing-Mean Sha:
Efficient feasibility analysis of DAG scheduling with real-time constraints in the presence of faults. ASP-DAC 2014: 131-136 - [c28]Liang Shi, Kaijie Wu, Mengying Zhao, Chun Jason Xue
Retention Trimming for Wear Reduction of Flash Memory Storage Systems. DAC 2014: 146:1-146:6 - [c27]Xiaotong Cui
High-Level Synthesis for Run-Time Hardware Trojan Detection and Recovery. DAC 2014: 157:1-157:6 - [c26]Congming Gao, Liang Shi, Kaijie Wu, Chun Jason Xue
Exploit asymmetric error rates of cell states to improve the performance of flash memory storage systems. ICCD 2014: 202-207 - [c25]Congming Gao, Liang Shi, Mengying Zhao, Chun Jason Xue
Exploiting parallelism in I/O scheduling for access conflict minimization in flash-based solid state drives. MSST 2014: 1-11 - [c24]Wendi Nie, Yaoxin Duan
Energy efficient routing techniques with guaranteed reliability based on multi-level uncertain graph. RTCSA 2014: 1-9 - [c23]Edwin Hsing-Mean Sha, Jörg Henkel, Kaijie Wu, Tarek F. Abdelzaher, Hojung Cha:
Messages from the conference chairs. RTCSA 2014: 1 - 2013
- [c22]Kaijie Wu, Shawn Patrick Casey, Lei Zhao, Xinyu Chai:
A method for construction of Nitinol antenna for implantable medical devices. BMEI 2013: 265-269 - 2012
- [j17]Tongquan Wei, Piyush Mishra, Kaijie Wu, Junlong Zhou:
Quasi-static fault-tolerant scheduling schemes for energy-efficient hard real-time systems. J. Syst. Softw. 85(6): 1386-1399 (2012) - [j16]Kun Ma, Han Liang, Kaijie Wu:
Homomorphic Property-Based Concurrent Error Detection of RSA: A Countermeasure to Fault Attack. IEEE Trans. Computers 61(7): 1040-1049 (2012) - 2011
- [j15]Yu Liu, Kaijie Wu, Ramesh Karri
Scan-based attacks on linear feedback shift register based stream ciphers. ACM Trans. Design Autom. Electr. Syst. 16(2): 20:1-20:15 (2011) - [c21]Kun Ma, Kaijie Wu:
LOEDAR: A low cost error detection and recovery scheme for ECC. DATE 2011: 1010-1015 - [c20]Yu Liu, Kaijie Wu:
Runtime adaptable concurrent error detection for linear digital systems. ICCD 2011: 261-266 - 2010
- [c19]Yu Liu, Han Liang, Kaijie Wu:
Scheduling for energy efficiency and fault tolerance in hard real-time systems. DATE 2010: 1444-1449 - [c18]Yu Liu, Kaijie Wu:
Towards cool and reliable digital systems: RT level CED techniques with runtime adaptability. ICCD 2010: 528-533
2000 – 2009
- 2009
- [c17]Yu Liu, Kaijie Wu:
An ILP formulation to Unify Power Efficiency and Fault Detection at Register-Transfer Level. DFT 2009: 349-357 - [i2]Yu Liu, Kaijie Wu, Ramesh Karri
Scan-based Attacks on Linear Feedback Shift Register Based Stream Ciphers. IACR Cryptol. ePrint Arch. 2009: 584 (2009) - 2008
- [j14]Tongquan Wei, Piyush Mishra, Kaijie Wu, Han Liang:
Fixed-Priority Allocation and Scheduling for Energy-Efficient Fault Tolerance in Hard Real-Time Multiprocessor Systems. IEEE Trans. Parallel Distributed Syst. 19(11): 1511-1526 (2008) - 2007
- [j13]Han Liang, Piyush Mishra, Kaijie Wu:
Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique. IEEE Trans. Computers 56(2): 243-252 (2007) - [j12]Kyosun Kim, Kaijie Wu, Ramesh Karri
The Robust QCA Adder Designs Using Composable QCA Building Blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1): 176-183 (2007) - [c16]Richard Stern, Nikhil Joshi, Kaijie Wu, Ramesh Karri
Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations. FDTC 2007: 112-119 - 2006
- [j11]Kyosun Kim, Kaijie Wu, Ramesh Karri
Quantum-Dot Cellular Automata Design Guideline. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(6): 1607-1614 (2006) - [j10]Nikhil Joshi, Jayachandran Sundararajan, Kaijie Wu, Bo Yang, Ramesh Karri
Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks. IEEE Trans. Computers 55(10): 1230-1239 (2006) - [j9]Kaijie Wu, Ramesh Karri
Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 413-422 (2006) - [j8]Nikhil Joshi, Kaijie Wu, Jayachandran Sundararajan, Ramesh Karri
Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1163-1169 (2006) - [j7]Bo Yang, Kaijie Wu, Ramesh Karri
Secure Scan: A Design-for-Test Architecture for Crypto Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2287-2293 (2006) - [c15]Tongquan Wei, Piyush Mishra, Kaijie Wu, Han Liang:
Online task-scheduling for fault-tolerant low-energy real-time systems. ICCAD 2006: 522-527 - 2005
- [c14]Tongquan Wei, Kaijie Wu, Ramesh Karri
Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands. ASP-DAC 2005: 1192-1195 - [c13]Bo Yang, Kaijie Wu, Ramesh Karri
Secure scan: a design-for-test architecture for crypto chips. DAC 2005: 135-140 - [c12]Kyosun Kim, Kaijie Wu, Ramesh Karri
Towards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths. DATE 2005: 1214-1219 - 2004
- [j6]Kaijie Wu, Ramesh Karri
Fault secure datapath synthesis using hybrid time and hardware redundancy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(10): 1476-1485 (2004) - [c11]Nikhil Joshi, Kaijie Wu, Ramesh Karri:
Concurrent Error Detection Schemes for Involution Ciphers. CHES 2004: 400-412 - [c10]Bo Yang, Kaijie Wu, Ramesh Karri
Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard. ITC 2004: 339-344 - [c9]Kaijie Wu, Ramesh Karri
Low Cost Concurrent Error Detection for the Advanced Encryption Standard. ITC 2004: 1242-1248 - [i1]Bo Yang, Kaijie Wu, Ramesh Karri
Scan Based Side Channel Attack on Data Encryption Standard. IACR Cryptol. ePrint Arch. 2004: 83 (2004) - 2003
- [j5]Kaijie Wu, Piyush Mishra, Ramesh Karri
Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit RC6 block cipher. Microelectron. J. 34(1): 31-39 (2003) - [j4]Kaijie Wu, Ramesh Karri
Selectively breaking data dependences to improve the utilization of idle cycles in algorithm level re-computing data paths. IEEE Trans. Reliab. 52(4): 501-511 (2003) - [c8]Kaijie Wu, Ramesh Karri
Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis. ITC 2003: 902-911 - 2002
- [j3]Kaijie Wu, Ramesh Karri
Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(9): 1077-1087 (2002) - [j2]Ramesh Karri
Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12): 1509-1517 (2002) - [j1]Ramesh Karri
Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 864-875 (2002) - [c7]Kaijie Wu, Ramesh Karri
Exploiting Idle Cycles for Algorithm Level Re-Computing. DATE 2002: 842-846 - 2001
- [c6]Ramesh Karri
Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers. DAC 2001: 579-585 - [c5]Kaijie Wu, Ramesh Karri
Idle Cycles Based Concurrent Error Detection of RC6 Encryption. DFT 2001: 200-205 - [c4]Ramesh Karri
Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture. DFT 2001: 427-435 - [c3]Kaijie Wu, Ramesh Karri
Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique. ICCAD 2001: 537- - [c2]Kaijie Wu, Ramesh Karri
Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique. ITC 2001: 221-229 - 2000
- [c1]Ramesh Karri
Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique. ITC 2000: 971-978
Coauthor Index
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