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Arunkumar Vijayakumar
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2010 – 2019
- 2019
- [i1]Arunkumar Vijayakumar, Vinay C. Patil, Daniel E. Holcomb, Christof Paar, Sandip Kundu:
Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device- and Logic-Level Techniques. CoRR abs/1910.00981 (2019) - 2017
- [j1]Arunkumar Vijayakumar
, Vinay C. Patil
Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques. IEEE Trans. Inf. Forensics Secur. 12(1): 64-77 (2017) - [c14]Vinay C. Patil, Arunkumar Vijayakumar, Daniel E. Holcomb, Sandip Kundu:
Improving reliability of weak PUFs via circuit techniques to enhance mismatch. HOST 2017: 146-150 - 2016
- [c13]Vinay C. Patil, Arunkumar Vijayakumar, Sandip Kundu:
On meta-obfuscation of physical layouts to conceal design characteristics. DFT 2016: 147-152 - [c12]Arunkumar Vijayakumar, Vinay C. Patil, Charles B. Prado, Sandip Kundu:
Machine learning resistant strong PUF: Possible or a pipe dream? HOST 2016: 19-24 - [c11]Vinay C. Patil, Arunkumar Vijayakumar, Sandip Kundu:
Preventing integrated circuit piracy via custom encoding of hardware instruction set. ISQED 2016: 234-241 - [c10]Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu:
On testing physically unclonable functions for uniqueness. ISQED 2016: 368-373 - [c9]Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu:
An Efficient Method for Clock Skew Scheduling to Reduce Peak Current. VLSID 2016: 505-510 - 2015
- [c8]Arunkumar Vijayakumar, Sandip Kundu:
A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics. DATE 2015: 653-658 - 2014
- [c7]Siva Nishok Dhanuskodi, Arunkumar Vijayakumar, Sandip Kundu:
A Chaotic Ring oscillator based Random Number Generator. HOST 2014: 160-165 - [c6]Arunkumar Vijayakumar, Vinay C. Patil, Girish Paladugu, Sandip Kundu:
On pattern generation for maximizing IR drop. ISQED 2014: 731-737 - [c5]Arunkumar Vijayakumar, Sandip Kundu:
Glitch Power Reduction via Clock Skew Scheduling. ISVLSI 2014: 504-509 - [c4]Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu:
On Maximizing Decoupling Capacitance of Clock-Gated Logic for Robust Power Delivery. ISVLSI 2014: 510-515 - 2013
- [c3]Arunachalam Annamalai, Raghavan Kumar, Arunkumar Vijayakumar, Sandip Kundu:
A system-level solution for managing spatial temperature gradients in thinned 3D ICs. ISQED 2013: 88-95 - 2012
- [c2]Arunkumar Vijayakumar, Raghavan Kumar, Sandip Kundu:
On Design of Low Cost Power Supply Noise Detection Sensor for Microprocessors. ISVLSI 2012: 120-125 - 2011
- [c1]Sudarshan Srinivasan, Bharath Phanibhushana, Arunkumar Vijayakumar, Sandip Kundu:
Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits. ACM Great Lakes Symposium on VLSI 2011: 265-270
Coauthor Index
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