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"A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High ..."

Kyung-Soo Ha et al. (2019)

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DOI: 10.1109/ISSCC.2019.8662509

access: closed

type: Conference or Workshop Paper

metadata version: 2024-03-05

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  - conf/isscc/HaLLMJHCPSPKLPC19
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  - https://dblp.org/rec/conf/isscc/HaLLMJHCPSPKLPC19
Kyung-Soo Ha, Chang-Kyo Lee, Dongkeon Lee, Daesik Moon, Jin-Hun Jang, Hyong-Ryol Hwang, Hyung-Joon Chi, Junghwan Park, Seungjun Shin, Dukha Park, Sang-Yun Kim, Sukhyun Lim, Kiwon Park, YeonKyu Choi, Young-Hwa Kim, Younghoon Son, Hyunyoon Cho, Byongwook Na, Hyo-Joo Ahn, Seungseob Lee, Seouk-Kyu Choi, Youn-Sik Park, Seok-Hun Hyun, Soobong Chang, Hyuck-Joon Kwon, Jung-Hwan Choi, Tae-Young Oh, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang:
A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. ISSCC 2019: 378-380

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