• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 14 matches

• 2024
• 
  Anis Hamadouche, Yun Wu, Mathini Sellathurai, Andrew M. Wallace, João F. C. Mota:
  Reconfigurable FPGA-Based Solvers For Sparse Satellite Control. CoRR abs/2406.00402 (2024)
• 2022
• 
  Christopher Chuvalas, Ranga Vemuri:
  FPGA-Based Stochastic Local Search Satisfiability Solvers Exploiting High Bandwidth Memory. VLSI-SoC 2022: 1-6
• 2021
• 
  Anh Hoang Ngoc Nguyen, Yuko Hara-Azumi:
  An FPGA-based Stochastic SAT Solver Leveraging Inter-Variable Dependencies. FPL 2021: 179-184
• 2020
• 
  Anh Hoang Ngoc Nguyen, Masashi Aono, Yuko Hara-Azumi:
  FPGA-Based Hardware/Software Co-Design of a Bio-Inspired SAT Solver. IEEE Access 8: 49053-49065 (2020)
• 2019
• 
  Anh Hoang Ngoc Nguyen, Masashi Aono, Yuko Hara-Azumi:
  FPGA-Based amoeba-inspired SAT solver for cyber-physical systems. ICCPS 2019: 316-317
• 2018
• 
  Anping He, Lvying Yu, Haitao Zhang, Lian Li, Jinzhao Wu:
  A FPGA Based SAT Solver with High Random and Concurrent Strategies. QRS Companion 2018: 221-228
• 2017
• 
  Khadija Bousmar, Fabrice Monteiro, Zineb Habbas, Sofiène Dellagi, Abbas Dandache:
  A pure hardware k-SAT solver architecture for FPGA based on generic tree-search. ICM 2017: 1-5
• 2015
• 
  Khadija Bousmar, Fabrice Monteiro, Zineb Habbas, Sofiène Dellagi, Abbas Dandache:
  A new FPGA-based DPLL algorithm to improve SAT solvers. ICM 2015: 287-290
• 2010
• 
  Leopold Haller, Satnam Singh:
  Relieving capacity limits on FPGA-based SAT-solvers. FMCAD 2010: 217-220
• 2006
• 
  Mona Safar, M. Watheq El-Kharashi, Ashraf Salem:
  FPGA-Based SAT Solver. CCECE 2006: 1901-1904
• 2005
• 
  Mona Safar, M. Watheq El-Kharashi, Ashraf Salem:
  FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers. CHARME 2005: 384-387
• 2002
• 
  Andreas Dandalis, Viktor K. Prasanna:
  Run-time performance optimization of an FPGA-based deduction engine for SAT solvers. ACM Trans. Design Autom. Electr. Syst. 7(4): 547-562 (2002)
• 2001
• 
  Andreas Dandalis, Viktor K. Prasanna, Bharani Thiruvengadam:
  Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers. FPL 2001: 315-325
• 1999
• 
  Pak K. Chan, Mark J. Boyd, Sezer Gören, K. Klenk, V. Kodavati, R. Kundu, M. Margolese, J. Sun, Katsuharu Suzuki, E. Thorne, X. Wang, J. Xu, M. Zhu:
  Reducing Compilation Time of Zhong's FPGA-Based SAT Solver. FCCM 1999: 308-309