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A-SSCC 2018: Tainan, Taiwan
- IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, November 5-7, 2018. IEEE 2018, ISBN 978-1-5386-6413-1
- Lu Lu, Taegeun Yoo, Van Loi Le, Tony Tae-Hyoung Kim:
An Ultra-low Power 8T SRAM with Vertical Read Word Line and Data Aware Write Assist. 1-2 - Kevin Zhang:
Circuit Design in Nano-Scale CMOS Technologies. 1-4 - Yosuke Toyama, Kentaro Yoshioka
, Koichiro Ban, Akihide Sai, Kohei Onizuka:
A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications. 1-4 - Xinchao Shang, Weiwei Shan, Jiaming Xu, Minyi Lu, Yiming Xiang, Longxing Shi, Jun Yang:
A 0.46V-1.1V Transition-Detector with In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in AES Accelerator. 1-4 - Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
An 11b 1GS/s Time-Interleaved ADC with Linearity Enhanced T/H. 1-2 - Himanshu Kaul, Mark A. Anders, Sanu Mathew, Vikram B. Suresh, Sudhir Satpathy, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS. 1-4 - Shenggao Li
A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS. 5-8 - Seizo Onoe:
Open the New World of 5G. 5-8 - Nam Sung Kim:
Practical Challenges in Supporting Function in Memory. 9-12 - Yoshisato Yokoyama, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Makoto Yabuuchi, Yuichiro Ishii, Koji Nii:
40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications. 9-12 - Yi Kang:
AI Drives Domain Specific Processors. 13-16 - Chien-An Lai, Chung-Cheng Chou, Chi-Hsiang Weng, Zheng-Jun Lin, Pei-Ling Tseng, Chien-Fan Wang, Chih-Chen Wang, Chin-I Su, Wei-Chi Chen, Yu-Cheng Lin, Tong-Chern Ong, Chi Chang, Yu-Der Chih, Tsung-Yung Jonathan Chang:
Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window. 13-16 - Chih-Wen Lu, You-Gang Chang, Xing-Wei Huang, Jhih-Siou Cheng, Po-Yu Tseng, Chih-Hsien Chou:
A 10-Bit 1026-Channel Column Driver IC with Partially Segmented Piecewise Linear Digital-to-Analog Converters for Ultra-High-Definition TFT-LCDs with One Billion Color Display. 17-20 - Neha Priyadarshini, Chandani Anand, Mukul Sarkar:
A WDR CMOS Image Sensor Employing In-pixel Capacitive Variation using a Re-configurable Source Follower for Low Light Applications. 21-24 - Hsiang-Lin Chen, Sung-En Hsieh, Tzu-Hsiang Hsu
A CMOS Imager for Reflective Pulse Oximeter with Motion Artifact and Ambient Interference Rejections. 25-26 - Reza Ranjandish
A 4-channel 5.04 μW 0.325 mm2 Orthogonal Sampling-Based Parallel Neural Recording System. 27-30 - U. Fat Chio, Kuo-Chih Wen, Sai-Weng Sin
An Integrated DC-DC Converter with Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery. 31-32 - Karim Rawy, Ruchi Sharma, Hong-Joon Yoon, Usman Khan, Sang-Woo Kim
An 88% Efficiency 2.4μW to 15.6μW Triboelectric Nanogenerator Energy Harvesting System Based on a Single-Comparator Control Algorithm. 33-36 - I-Che Ou
A Wide-Range Capacitive DC-DC Converter with 2D-MPPT for Soil/Solar Energy Extraction. 37-38 - Ye-Sing Luo, Hsing-Hung Lin, Shen-Iuan Liu:
A 13.56 MHz 88.7%-PCE Voltage Doubling Rectifier Using Adaptive Delay Time and Pulse-Width Control. 39-42 - Jan A. Angevare, Kofi A. A. Makinwa:
A 6800-μm2 Resistor-Based Temperature Sensor in 180-nm CMOS. 43-46 - Asuka Maki, Daisuke Miyashita, Kengo Nakata, Fumihiko Tachibana, Tomoya Suzuki, Jun Deguchi:
FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision. 47-50 - Weijia Chen, Hui Wu, Shaojun Wei, Anping He, Hong Chen:
An Asynchronous Energy-Efficient CNN Accelerator with Reconfigurable Architecture. 51-54 - Koichi Mitsunari, Jaehoon Yu, Masanori Hashimoto
Hardware Architecture for Fast General Object Detection using Aggregated Channel Features. 55-58 - Val Mikos, Chun-Huat Heng, Arthur Tay
A Neural Network Accelerator With Integrated Feature Extraction Processor for a Freezing of Gait Detection System. 59-62 - Yoshihide Komatsu, Akinori Shinmyo, Masami Funabashi, Shuji Kato, Kazuya Hatooka, Kenji Tanaka, Mayuko Fujita, Kouichi Fukuda:
A 0.25-27Gb/s Wideband PAM4/NRZ Transceiver with Adaptive Power CDR for 8K System. 63-66 - Juncheng Wang, Xuefeng Chen, Shang Hu
A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver designed in 40nm-CMOS. 67-68 - Akitaka Hiratsuka, Akira Tsuchiya, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka
A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation. 69-72 - Min-Seong Choo
A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop. 73-76 - Jian Pang, Korkut Kaan Tokgoz
A 28.16-Gb/s Area-Efficient 60GHz CMOS Bi-Directional Transceiver for IEEE 802.11ay. 77-78 - Jianxi Wu, Zipeng Chen, Wei Zheng, Yibo Liu, Shufu Wang, Nan Qi, Baoyong Chi:
A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC with Dual Rising-Edge Fractional-Phase Detector. 79-82 - Taikun Ma, Zipeng Chen, Jianxi Wu, Wei Zheng, Shufu Wang, Nan Qi, Baoyong Chi:
A CMOS 76-81 GHz 2TX 3RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator. 83-86 - Tong Fang
A 25 fps 32 × 24 Digital CMOS Terahertz Image Sensor. 87-90 - Hyuntak Jeon, Jun-Suk Bang, Yoontae Jung, Taeju Lee, Yeseul Jeon, Seok-Tae Koh, Jaesuk Choi, Doojin Jang, Soonyoung Hong, Minkyu Je:
A 3.9μW, 81.3dB SNDR, DC-coupled, Time-based Neural Recording IC with Degeneration R-DAC for Bidirectional Neural Interface in 180nm CMOS. 91-92 - Yi Zhong
A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS. 93-94 - Hongrui Luo, Quan Sun, Ruizhi Zhang, Hong Zhang:
A 1-V 3.1-ppm/°C 0.8-μW Bandgap Reference with Piecewise Exponential Curvature Compensation. 97-98 - Matthias Eberlein
A 40nW, Sub-IV Truly 'Digital' Reverse Bandgap Reference Using Bulk-Diodes in 16nm FinFET. 99-102 - Yao-Sheng Hu, Li-Yu Huang, Hsin-Shu Chen:
A 0.6V 1.63fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System. 103-106 - Pengcheng Xu, Denis Flandre, David Bol:
Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT smart sensors. 107-110 - Jianming Zhao, Yuan Gao
A 6.78-200 MHz Offset-Compensated Active Rectifier with Dynamic Logic Comparator for mm-size Wirelessly Powered Implants. 111-114 - Ren Usami, Takao Komiyama, Yasunori Chonan, Hiroyuki Yamaguchi, Koji Kotani:
Photovoltaic-Assisted Self-Vth-Cancellation CMOS RF Rectifier for Wide Power Range Operation. 115-118 - Masoud Seifaei
Stable, Self-Biased and High-Gain Organic Amplifiers with Reduced Parameter Variation Effect. 119-122 - Vinod V. Gadde, Hiromitsu Awano
An Encryption-Authentication Unified A/D Conversion Scheme for IoT Sensor Nodes. 123-126 - Cheng-Xin Xue, Wei-Cheng Zhao, Tzu-Hsien Yang, Yi-Ju Chen, Hiroyuki Yamauchi
A 28mn 320Kb TCAM Macro with Sub-0.8ns Search Time and 3.5+x Improvement in Delay-Area-Energy Product using Split-Controlled Single-Load 14T Cell. 127-128 - Kota Tsurumi, Kenta Suzuki, Ken Takeuchi:
A 6.8 TOPS/W Energy Efficiency, 1.5µW Power Consumption, Pulse Width Modulation Neuromorphic Circuits for Near-Data Computing with SSD. 129-132 - Trang Le Dinh Dang
A 28mn FD-SOI 4KB Radiation-hardened 12T SRAM Macro with 0.6 ~ 1V Wide Dynamic Voltage Scaling for Space Applications. 133-134 - Keji Zhou
Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F2 and K-means Clustering for Power Reduction. 135-138 - Joung-Wook Moon, Hye-Sung Yoo, Hundai Choi, Il-Won Park, Seok-Yong Kang, Jun-Bae Kim, Haeyoung Chung, Kiho Kim, Dong-Hun Lee, Ki-Jae Song, Seok-Hun Hyun, Indal Song, Young-Soo Sohn, Yong-Ho Cho, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang:
An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM. 139-142 - Shotaro Sugiyama, Hiromitsu Awano
31.3 μs/Signature-Generation 256-bit 픽p ECDSA Cryptoprocessor. 153-156 - Kai-Hsin Chuang, Erik Bury, Robin Degraeve, Ben Kaczer, Dimitri Linten, Ingrid Verbauwhede
A Physically Unclonable Function with 0% BER Using Soft Oxide Breakdown in 40nm CMOS. 157-160 - Kunyang Liu
A 373 F2 2D Power-Gated EE SRAM Physically Unclonable Function With Dark-Bit Detection Technique. 161-164 - Chih-Lun Lo, Hao-Chung Cheng, Pei-Chun Liao, Yi-Lun Chen, Po-Hung Chen:
An 82.1%-Power-Efficiency Single-Inductor Triple-Source Quad-Mode Energy Harvesting Interface with Automatic Source Selection and Reversely Polarized Energy Recycling. 165-168 - Mao-Ling Chiu, Tzu-Hsuan Yang, Tsung-Hsien Lin:
A Transient-Enhanced Constant On-Time Buck Converter with Light-Load Efficiency Optimization. 169-170 - Chao-Jen Huang, Yao-Sheng Ma, Wen-Hau Yang, Yen-Ting Lin, Chun-Chieh Kuo, Ke-Horng Chen
A 99.2% Tracking Accuracy Single-Inductor Quadruple-Input-Quadruple-Output Buck-Boost Converter Topology with Periodical Interval Perturbation and Observation MPPT. 171-174 - Kai-Yu Hu, Yu-Sin Chen, Chien-Hung Tsai:
A Digital Multiphase Converter with Sensor-less Current and Thermal Balance Mechanism. 175-178 - Tianyu Jia, Jie Gu:
A Fully-integrated LC-Oscillator Based Buck Regulator with Autonomous Resonant Switching for Low-Power Applications. 179-182 - Pranay Prabhat
A bulk 65nm Cortex-M0+ SoC with All-Digital Forward Body Bias for 4.3X Subthreshold Speedup. 183-186 - Po-Wei Chiu, Muqing Liu, Qianying Tang, Chris H. Kim:
A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer. 187-190 - Guiqiang Peng, Leibo Liu
A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems. 191-194 - Mitsuhiko Igarashi
A Fully Standard-Cell Based On-Chip BTI and HCI Monitor with 6.2x BTI sensitivity and 3.6x HCI sensitivity at 7 nm Fin-FET Process. 195-196 - Guenole Lallement, Fady Abouzeid
A 140 nW, 32.768 kHz, 1.9 ppm/°C Leakage-Based Digitally Relocked Clock Reference with 0.1 ppm Long-Term Stability in 28nm FD-SOI. 197-200 - Seuk Son, Hwanseok Yeo, Sigang Ryu, Jaeha Kim:
A 2× Blind Oversampling FSE Receiver with Combined Adaptive Equalization and Infinite-Range Timing Recovery. 201-204 - Masum Hossain, Aurangozeb
A Bimodal (NRZ/PAM-4) ISI Tolerant Timing Recovery with Adaptive DDJ Equalization. 205-208 - Minsoo Choi, Myungguk Lee, Byungsub Kim:
A 12-Gb/s AC-Coupled FFE TX With Adaptive Relaxed Impedance Matching Achieving Adaptation Range of 35-75Ω Z0 and 30-550Ω RRX. 209-212 - Chia-Tse Hung, Yu-Ping Huang, Wei-Zen Chen:
A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking. 213-214 - Jingcheng Tao, Chun-Huat Heng:
A 1.6-GHz 3.3-mW 1.5-MHz Wide Bandwidth ΔΣ Fractional-N PLL with a Single Path FIR Phase Noise Filtering. 215-218 - Sangyeop Lee, Kyoya Takano
A 37-GHz-Input Divide-by-36 Injection-Locked Frequency Divider with 1.6-GHz Lock Range. 219-222 - Luya Zhang
A 37.5-45. lGHz Superharmonic-Coupled QVCO with Tunable Phase Accuracy in 28nm Bulk CMOS. 223-226 - Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu, Nanjian Wu:
A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range. 227-230 - Matan Gal-Katziri, Ali Hajimiri:
A Sub-Picosecond Hybrid DLL for Large-Scale Phased Array Synchronization. 231-234 - Wenning Jiang
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler. 235-238 - Il-Min Yi, Naoki Miura, Hiroyuki Fukuyama, Hideyuki Nosaka
A 15.1-mW 6-GS/s 6-bit Flash ADC with Selectively Activated 8× Time-Domain Interpolation. 239-242 - Yung-Hui Chung, Chia-Yi Hu, Che-Wei Chang:
A 38-mW 7-bit 5-GS/s Time-Interleaved SAR ADC with Background Skew Calibration. 243-246 - Young-Ha Hwang
A 0.6-to-1V 10k-to-100kHz BW 11.7b-ENOB Noise-Shaping SAR ADC for IoT sensor applications in 28-nm CMOS. 247-248 - Kwuang-Han Chang, Chih-Cheng Hsieh:
A Calibration-Free 0.7-V 13-bit 10-MS/s Full-Analog SAR ADC with Continuous-Time Feedforward Cascaded (CTFC) Op-Amps. 249-252 - Yao-Sheng Hu, Jhao-Huei Lin, Ding-Guo Lin, Kai-Yue Lin, Hsin-Shu Chen:
An 89.55dB-SFDR 179.6dB-FoMs 12-bit lMS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration. 253-256 - Zhengyu Chen, Jie Gu:
An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation. 257-260 - Li-De Chen, Yu-Ta Lu, Yu-Ling Hsiao, Bo-Hsiang Yang, Wei-Chi Chen, Chao-Tsung Huang:
A 95pJ/label Wide-Range Depth-Estimation Processor for Full-HD Light-Field Applications on FPGA. 261-262 - Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Vinodh Gopal, James Guilford, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS. 263-266 - Syed Muhammad Abubakar, Muhammad Rizwan Khan
A Wearable Auto-Patient Adaptive ECG Processor for Shockable Cardiac Arrhythmia. 267-268 - Mitsuru Hiraki, Sugako Otani, Masao Ito, Takuya Mizokami, Masahiro Araki, Hiroyuki Kondo:
A Capacitance-to-Digital Converter Integrated in a 32bit Microcontroller for 3D Gesture Sensing. 269-272 - Luke R. Everson, Muqing Liu, Nakul Pande, Chris H. Kim:
A 104.8TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nm. 273-276 - Taegeun Yoo, Van Loi Le, Ju Eon Kim, Ngoc Le Ba, Kwang-Hyun Baek, Tony T. Kim:
A 137-μW Area-Efficient Real-Time Gesture Recognition System for Smart Wearable Devices. 277-280 - Hye-Yeon Yoon, Seung-Jun Hwang, Tae-Hwan Kim:
A 655Mbps Successive-Cancellation Decoder for a 1024-bit Polar Code in 180nm CMOS. 281-284 - Stevo Bailey, Jaeduk Han, Paul Rigge, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic
A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET. 285-288 - Shihai He
A Compact High Efficiency and High Power Front-end Module for GSM/EDGE/TD-SCDMA/TD-LTE Applications in 0.13um CMOS. 289-292 - Kai Xu, Jun Yin
A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNA. 293-294 - Haixin Song, Dang Liu, Woogeun Rhee
A 6-8GHZ 200MHz Bandwidth 9-Channel VWB Transceiver with 8 Frequency-Hopping Subbands. 295-298 - Jaewon Choi, Nam-Seog Kim, Juyoung Han, Thomas Byunghak Cho:
A 0.46-2.1 GHz Spurious and Oscillator-Pulling Free LO Generator for Cellular NB-IoT Transmitter with 23 dBm Integrated PAs in 28nm CMOS. 299-302 - Avish Kosari, Milad Moosavifar
A 152μW -99dBm BPSK/16-QAM OFDM Receiver for LPWAN Applications. 303-306
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