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ISSCC 2009: San Francisco, CA, USA
- IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009. IEEE 2009, ISBN 978-1-4244-3458-9
Paper Sessions
Plenary Session
- René Penning de Vries, William Redman-White, Raf Roovers, Leo Warmerdam, Ted Letavic:
Leaner and greener: Adapting to a changing climate of innovation. 8-13 - Kiyoo Itoh:
Adaptive circuits for the 0.5-V nanoscale CMOS era. 14-20 - Mark Bohr:
The new era of scaling in an SoC world. 23-28 - John Cohn:
Kids today! Engineers tomorrow? 29-35
Imagers
- Vyshnavi Suntharalingam, Robert Berger, Stewart Clark, Jeffrey M. Knecht, Andrew Messier, Kevin Newcomb, Dennis Rathman, Richard Slattery, Antonio M. Soares, Charles Stevenson, Keith Warner, Douglas Young, Lin Ping Ang, Barmak Mansoorian
, David C. Shaver:
A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor. 38-39 - Lucio Carrara, Cristiano Niclass, Noémy Scheidegger, Herbert Shea
A gamma, x-ray and high energy proton radiation-tolerant CIS for space applications. 40-41 - Ronald Kapusta
A 4-channel 20-to300 Mpixel/s analog front-end with sampled thermal noise below kT/C for digital SLR cameras. 42-43 - Nagataka Tanaka, Junji Naruse, Akiko Mori, Ryuta Okamoto, Hirofumi Yamashita, Makoto Monoi:
A 1/2.5-inch 8Mpixel CMOS image sensor with a staggered shared-pixel architecture and an FD-boost operation. 44-45 - Pierre-François Rüedi, Pascal Heim, Steve Gyger, François Kaess, Claude Arm, Ricardo Caseiro, Jean-Luc Nagel, Silvio Todeschini:
An SoC combining a 132dB QVGA pixel array and a 32b DSP/MCU processor for vision applications. 46-47 - Ryu Shimizu, Mamoru Arimoto, Hayato Nakashima, Kaori Misawa, Kazuhiro Suzuki, Toshikazu Ohno, Yugo Nose, Keisuke Watanabe, Tatsushi Ohyama, Kuniyuki Tani:
A charge-multiplication CMOS image sensor suitable for low-light-level imaging. 50-51 - Anthony Huggett, Chris Silsby, Sergi Cami, Jeff Beck:
A dual-conversion-gain video sensor with dewarping and overlay on a single chip. 52-53
Microprocessor Technologies
- Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli:
A 45nm 8-core enterprise Xeon® processor. 56-57 - Rajesh Kumar, Glenn Hinton:
A family of 45nm IA processors. 58-59 - Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno:
A chip-stacked memory for on-chip SRAM-rich SoCs and processors. 60-61 - Andrew Allen, Jay Desai, Frank Verdico, Ferd Anderson, David Mulvihill, Dan Krueger:
Dynamic frequency-switching clock system on a quad-core Itanium® processor. 62-63 - Carlos Tokunaga
Secure AES engine with a local switched-capacitor current equalizer. 64-65 - Byungsub Kim, Vladimir Stojanovic:
A 4Gb/s/ch 356fJ/b 10mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm CMOS. 66-67 - Kyoungho Woo, Scott E. Meninger, Thucydides Xanthopoulos, Ethan Crain, Dongwan Ha, Donhee Ham
Dual-DLL-based CMOS all-digital temperature sensor for microprocessor thermal monitoring. 68-69 - Ravi Kuppuswamy, Shankar R. Sawant, Srikanth Balasubramanian, Pradeep Kaushik, Narayanan Natarajan, Jeffrey D. Gilbert:
Over one million TPCC with a 45nm 6-core Xeon® CPU. 70-71
High-Speed Data Converters
- Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult:
A 12b 2.9GS/s DAC with IM3 ≪-60dBc beyond 1GHz in 65nm CMOS. 74-75 - Erkan Alpman, Hasnain Lakdawala, L. Richard Carley, Krishnamurthy Soumyanath:
A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS. 76-77 - Robert C. Taft, Pier Andrea Francese
A 1.8V 1.0GS/s 10b self-calibrating unified-folding-interpolating ADC with 9.1 ENOB at Nyquist frequency. 78-79 - Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang:
A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS. 80-81 - Wenbo Liu, Yuchun Chang, Szukang Hsien, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu
A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization. 82-83 - Ashutosh Verma, Behzad Razavi:
A 10b 500MHz 55mW CMOS ADC. 84-85 - Siddharth Devarajan, Larry Singer, Dan Kelly, Steven Decker, Abhishek Kamath, Paul Wilkins:
A 16b 125MS/s 385mW 78.7dB SNR CMOS pipeline ADC. 86-87
Potpourri: PLL, Optical, DSL
- Song-Yu Yang, Wei-Zen Chen:
A 7.1mW 10GHz all-digital frequency synthesizer with dynamically reconfigurable digital loop filter in 90nm CMOS. 90-91 - Jri Lee, Huaide Wang, Wen-Tsao Chen, Yung-Pin Lee:
Subharmonically injection-locked PLLs for ultra-low-noise clock generation. 92-93 - Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Jean-Olivier Plouchart, John F. Bulzacchelli, Zeynep Toprak Deniz, Daniel J. Friedman:
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications. 94-95 - Sujiang Rong, Alan W. L. Ng, Howard C. Luong
0.9mW 7GHz and 1.6mW 60GHz frequency dividers with locking-range enhancement in 0.13µm CMOS. 96-97 - Kyu-Hyoun Kim
A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS. 98-99 - Sushmit Goswami, Jason Silver, Tino Copani, Wenjian Chen, Hugh J. Barnaby, Bert Vermeire, Sayfe Kiaei:
A 14mW 5Gb/s CMOS TIA with gain-reuse regulated cascode compensation for parallel optical interconnects. 100-101 - Jisook Yun, Mikyung Seo, Boo-Young Choi, Jung-Won Han, Yunsung Eo, Sung Min Park:
A 4Gb/s current-mode optical transceiver in 0.18µm CMOS. 102-103 - Jun Terada, Yusuke Ohtomo, Kazuyoshi Nishimura, Hiroaki Katsurai, Shunji Kimura
Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit. 104-105 - Daisuke Watanabe, Atsushi Ono, Toshiyuki Okayasu:
CMOS optical 4-PAM VCSEL driver with modal-dispersion equalizer for 10Gb/s 500m MMF transmission. 106-107 - Giovanni Cesura, Alessandro Bosi, Francesco Rezzi, Rinaldo Castello
A VDSL2 CPE AFE in 0.15µm CMOS with integrated line driver. 108-109
Cellular and Tuner
- Rajasekhar Pullela, Shahrzad Tadjpour, Dmitriy Rozenblit, William Domino, Thomas Obkircher, Mohamed El Said, Bala Ramachandran, Tirdad Sowlati, Darioush Agahi, Wei-Hong Chen, Dean A. Badillo, Masoud Kahrizi, Jaleh Komaili, Stephane Wloczysiak, Utku Seckin, Yunyoung Choi, Hasan Akyol, Martin Vadkerti, Amir Mahjoob, Hamid Firouzkouhi, Dan Shum, Rajendra Suhanthan, Nooshin Vakilian, Tom Valencia, Christophe Dantec, Aaron Paff, Mona Ahooie:
An integrated closed-loop polar transmitter with saturation prevention and low-IF receiver for quad-band GPRS/EDGE. 112-113 - Olivier Gaborieau, Sven Mattisson, Nikolaus Klemmer, Bassem Fahs, Fabio T. Braz, Richard Gudmundsson, Thomas Mattsson, Carine Lascaux, Christophe Trichereau, Wen Suter, Eric Westesson, Andreas Nydahl:
A SAW-less multiband WEDGE receiver. 114-115 - Tirdad Sowlati, Bipul Agarwal, J. Cho, Thomas Obkircher, Mohamed El Said, John Vasa, Bala Ramachandran, Masoud Kahrizi, Elias Dagher, Wei-Hong Chen, Martin Vadkerti, Georgi Taskov, Utku Seckin, Hamid Firouzkouhi, Behzad Saeidi, Hasan Akyol, Yunyoung Choi, Amir Mahjoob, Sandeep D'Souza, Chieh-Yu Hsieh, David Guss, Dan Shum, Dean A. Badillo, Imtiyaz Ron, Doris Ching, Feng Shi, Yong He, Jaleh Komaili, Aravind Loke, Rajasekhar Pullela, Engin Pehlivanoglu, Hossein Zarei, Shahrzad Tadjpour, Darioush Agahi, Dmitriy Rozenblit, William Domino, Gregory Williams, Nader Damavandi, Stephane Wloczysiak, Suhanthan Rajendra, Aaron Paff, Tom Valencia:
Single-chip multiband WCDMA/HSDPA/HSUPA/EGPRS transceiver with diversity receiver and 3G DigRF interface without SAW filters in transmitter / 3G receiver paths. 116-117 - Aristotele Hadjichristos, Marco Cassia, Hong Sun Kim, C. H. Park, Kevin Wang, W. Zhuo, Bahman Ahrari, Roger Brockenbrough, J. Chen, Conor Donovan, R. Jonnalagedda, J. Kim, Jin-Su Ko, Hee Choul Lee, Sang Oh Lee, Emilia Lei, T. Nguyen, T. Pan, S. Sridhara, W. Su, H. Yan, J. Yang, Cormac Conroy, Charles J. Persico, Kamal Sahota, B. Kim:
Single-chip RF CMOS UMTS/EGSM transceiver with integrated receive diversity and GPS. 118-119 - Xin He, Jan van Sinderen:
A 45nm low-power SAW-less WCDMA transmit modulator using direct quadrature voltage modulation. 120-121 - Francesco Gatta, Ray Gomez, Young Shin, Takayuki Hayashi, Hanli Zou, James Y. C. Chang, Leonard Dauphinee, Jianhong Xiao, Dave S.-H. Chang, Tai-Hong Chih, Massimo Brandolini, Dongsoo Koh, Bryan Juo-Jung Hung, Tao Wu, Mattia Introini, Giuseppe Cusmai, Loke Tan, Bruce Currivan, Lin He, Peter Cangiane, Pieter Vorenkamp:
An embedded 65nm CMOS low-IF 48MHz-to-1GHz dual tuner for DOCSIS 3.0. 122-123 - Yi-Ti Huang, C. M. Yang, S. C. Huang, H. L. Pan, T. C. Hung:
A 1.2V 67mW 4mm2 mobile ISDB-T tuner in 0.13µm CMOS. 124-125
DRAM
- Yongsam Moon, Yong-Ho Cho, Hyun-Bae Lee, Byung-Hoon Jeong, Seok-Hun Hyun, Byungchul Kim, In-Chul Jeong, Seong-Young Seo, Junho Shin, Seok-Woo Choi, Ho-Sung Song, Jung-Hwan Choi, Kyehyun Kyung, Young-Hyun Jun, Kinam Kim:
1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture. 128-129 - Uksong Kang, Hoeju Chung, Seongmoo Heo, Soon-Hong Ahn, Hoon Lee, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jin Ho Kim, Jaewook Lee, Han-Sung Joo, Woo-Seop Kim, Hyun-Kyung Kim, Eun-Mi Lee, So-Ra Kim, Keum-Hee Ma, Dong-Hyun Jang, Nam-Seog Kim, Man-Sik Choi, Sae-Jang Oh, Jung-Bae Lee, Tae-Kyung Jung, Jei-Hwan Yoo, Changhyun Kim:
8Gb 3D DDR3 DRAM using through-silicon-via technology. 130-131 - Bong Hwa Jeong, Jongwon Lee, Yin Jae Lee, Tae Jin Kang, Joo Hyeon Lee, Duck Hwa Hong, Jae Hoon Kim, Eun Ryeong Lee, Min Chang Kim, Kyung Ha Lee, Sang Il Park, Jong Ho Son, Sang Kwon Lee, Seong Nyuh Yoo, Sung Mook Kim, Tae Woo Kwon, Jin-Hong Ahn, Yong Tak Kim:
A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application. 132-133 - Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein:
75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques. 134-135 - Hamid Partovi, Karthik Gopalakrishnan, Luca Ravezzi, Russell Homer, Otto Schumacher, Reinhold Unterricker, Werner Kederer:
Single-ended transceiver design techniques for 5.33Gb/s graphics applications. 136-137 - Kyung-Soo Ha, Lee-Sup Kim, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim:
A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces. 138-139 - Hyun-Woo Lee, Won-Joo Yun, Young-Kyoung Choi, Hyang-Hwa Choi, Jong-Jin Lee, Ki-Han Kim, Shin-Deok Kang, Ji-Yeon Yang, Jae-Suck Kang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung:
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS. 140-141 - Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh:
Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays. 142-143
Multimedia Processors
- Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha:
An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply. 146-147 - Yuya Hanai, Yuichi Hori, Jun Nishimura, Tadahiro Kuroda:
A versatile recognition processor employing Haar-like feature and cascaded classifier. 148-149 - Joo-Young Kim, Minsu Kim, Seungjin Lee, Jinwook Oh, Kwanho Kim, Sejong Oh, Jeong-Ho Woo, Donghyun Kim, Hoi-Jun Yoo:
A 201.4GOPS 496mW real-time multi-object recognition processor with bio-inspired neural perception engine. 150-151 - Chi-Cheng Ju, Tsu-Ming Liu, Chih-Chieh Yang, Shih-Hung Lin, Kuo-Pin Lan, Chien-Hua Wu, Ting-Hsun Wei, Chi-Chin Lien, Jiun-Yuan Wu, Chih-Hao Hsiao, Te-Wei Chen, Yeh-Lin Chu, Guan-Yi Lin, Yung-Chang Chang, Kung-Sheng Lin, Chih-Ming Wang, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Chien-Hung Lin, Yung-Teng Lin, Shang-Ming Lee, Ya-Ching Yang, Yu-Lun Cheng, Chen-Chia Lee, Ming-Shiang Lai, Wen-Hua Wu, Ted Hu, Chao-Wei Tseng, Chen-Yu Hsiao, Wei-Liang Lee, Bo-Jiun Chen, Pao-Cheng Chiu, Shang-Ping Chen, Kun-Hsien Li, Kuan-Hua Chao, Chien-Ming Chen, Chuan-Cheng Hsiao, Jeffrey Ju, Wei-Hung Huang, Chi-Hui Wang, Hung-Sung Li, Evan Su, Joe Chen:
A multi-format Blu-ray player SoC in 90nm CMOS. 152-153 - Li-Fu Ding, Wei-Yin Chen, Pei-Kuei Tsung, Tzu-Der Chuang, Hsu-Kuang Chiu, Yu-Han Chen, Pai-Heng Hsiao, Shao-Yi Chien
A 212MPixels/s 4096×2160p multiview video encoder chip for 3D/quad HDTV applications. 154-155 - Motoyasu Shirasaki, Yusaku Miyazaki, Masahiro Hoshaku, Hiroo Yamamoto, Sachio Ogawa, Takuya Arimura, Hiroshi Hirai, Yasuo Iizuka, Tsutomu Sekibe, Yoichi Nishida, Toshiyuki Ishioka, Junji Michiyama:
A 45nm single-chip application-and-baseband processor using an intermittent operation technique. 156-157 - Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori:
A 342mW mobile application processor with full-HD multi-standard video codec. 158-159
Data Converter Techniques
- Andrea Panigada, Ian Galton:
A 130mW 100MS/s pipelined ADC with 69dB SNDR enabled by digital harmonic distortion correction. 162-163 - Imran Ahmed, Jan Mulder, David A. Johns:
A 50MS/s 9.9mW pipelined ADC with 58dB SNDR in 0.18µm CMOS using capacitive charge-pumps. 164-165 - Lane Brooks, Hae-Seung Lee:
A 12b 50MS/s fully differential zero-crossing-based ADC without CMFB. 166-167 - Shahrzad Naraghi, Matthew Courcy, Michael P. Flynn:
A 9b 14µW 0.06mm2 PPM ADC in 90nm digital CMOS. 168-169 - Min C. Park, Michael H. Perrott:
A 0.13µm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based integrator and quantizer. 170-171 - Sheng-Jui Huang, Yung-Yu Lin:
A 1.2V 2MHz BW 0.084mm2 CT ΔΣ ADC with -97.7dBc THD and 80dB DR using low-latency DEM. 172-173 - Vijay Dhanasekaran, Manisha Gambhir, Mohamed M. Elsayed, Edgar Sánchez-Sinencio, José Silva-Martínez, Chinmaya Mishra, Lei Chen, Erik Pankratz:
A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element. 174-175 - Lynn Bos, Gerd Vandersteen, Julien Ryckaert, Pieter Rombouts, Yves Rolain, Geert Van der Plas
A multirate 3.4-to-6.8mW 85-to-66dB DR GSM/bluetooth/UMTS cascade DT ΔΣM in 90nm digital CMOS. 176-177
Multi-Gb/s Serial Links and Building Blocks
- Lidong Chen, Xuguang Zhang, Fulvio Spagna:
A Scalable 3.6-to-5.2mW 5-to-10Gb/s 4-tap DFE in 32nm CMOS. 180-181 - Yong Liu, Byungsub Kim, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman:
A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS. 182-183 - Seon-Kyoo Lee
A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate. 184-185 - Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Tatsuya Saito:
10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1st-order ΔΣ modulator. 186-187 - Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone:
A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control. 188-189 - Yan-Bin Luo, Ping Chen, Qui-Ting Chen, Chih-Yong Wang, Chan-Hao Chang, Szu-Jui Fu, Chien-Ming Chen, Hung-Sung Li:
A 250Mb/s-to-3.4Gb/s HDMI receiver with adaptive loop updating frequencies and an adaptive equalizer. 190-191 - Koichi Yamaguchi, Yoshihiko Hori, Keiichi Nakajima, Kazumasa Suzuki, Masayuki Mizuno, Hiroshi Hayama:
A 2.0Gb/s clock-embedded interface for full-HD 10b 120Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery. 192-193
TD: Trends in Wireless Communications
- Pierre Vincent, Marie Claire Cyrille, Bernard Viala, Bertrand Delaet, Jean-Philippe Michel, Patrick Villard, Jérôme Prouvée, Dimitri Houssameddine, Ursula Ebels, Jordan A. Katine, Daniele Mauri, Sylvia Florez, Ozhan Ozatay
A GHz spintronic-based RF oscillator. 196-197 - Majid Baghaei Nejad
A remote-powered RFID tag with 10Mb/s UWB uplink and -18.5dBm sensitivity UHF downlink in 0.18µm CMOS. 198-199 - Denis C. Daly, Patrick P. Mercier
A pulsed UWB receiver SoC for insect motion control. 200-201 - Swaminathan Sankaran, Chuying Mao, Eunyoung Seok, Dongha Shim, Changhua Cao, Ruonan Han, Daniel J. Arenas, David B. Tanner, Stephen Hill, Chih-Ming Hung
Towards terahertz operation of CMOS. 202-203 - Alberto Fazzi, Sotir Ouzounov, John van den Homberg:
A 2.75mW wideband correlation-based transceiver for body-coupled communication. 204-205 - Kris Myny
A 128b organic RFID transponder chip, including Manchester encoding and ALOHA anti-collision protocol, operating with a data rate of 1529b/s. 206-207 - Robert Blache, Jürgen Krumm, Walter Fix:
Organic CMOS circuits for RFID applications. 208-209 - David Ruffieux, Aurélie Pezous, Anne-Claire Pliska, François Krummenacher:
Silicon-resonator-based, 3µA real-time clock with ±5ppm frequency accuracy. 210-211 - Shailesh Rai, Jeremy Holleman, Jagdish Nayayan Pandey, Fan Zhang, Brian P. Otis:
A 500µW neural tag with 2µVrms AFE and frequency-multiplying MICS/ISM FSK transmitter. 212-213
RF Building Blocks
- Daniele Mastantuono, Danilo Manstretta
A low-noise active balun with IM2 cancellation for multiband portable DVB-H receivers. 216-217 - Sanghyun Woo, Woonyun Kim, Chang-Ho Lee, Kyutae Lim, Joy Laskar:
A 3.6mW differential common-gate CMOS LNA with positive-negative feedback. 218-219 - Yu-Jiu Wang, Ali Hajimiri
A compact low-noise weighted distributed amplifier in CMOS. 220-221 - Michiel C. M. Soer, Eric A. M. Klumperink, Zhiyu Ru, Frank E. van Vliet, Bram Nauta
A 0.2-to-2.0GHz 65nm CMOS receiver without LNA achieving ≫11dBm IIP3 and ≪6.5 dB NF. 222-223 - Jun Deguchi, Daisuke Miyashita, Mototsugu Hamada:
A 0.6V 380µW -14dBm LO-input 2.4GHz double-balanced current-reusing single-gate CMOS mixer with cyclic passive combiner. 224-225 - Stefano Pellerano, Paolo Madoglio, Yorgos Palaskas:
A 4.75GHz fractional frequency divider with digital spur calibration in 45nm CMOS. 226-227 - Emanuele Lopelli, Johan van der Tang, Kathleen Philips, Arthur H. M. van Roermund, Bert Gyselinckx:
A 0.75V 325µW 40dB-SFDR frequency-hopping synthesizer for wireless sensor networks in 90nm CMOS. 228-229 - Zhiyu Ru, Eric A. M. Klumperink, Gerard Wienk, Bram Nauta
A software-defined radio receiver architecture robust to out-of-band interference. 230-231 - Niels A. Moseley, Zhiyu Ru, Eric A. M. Klumperink, Bram Nauta
A 400-to-900 MHz receiver with dual-domain harmonic rejection exploiting adaptive interference cancellation. 232-233
Flash Memory
- Raymond Zeng, Navneet Chalagalla, Dan Chu, Daniel Elmhurst, Matt Goldman, Chris Haid, Atif Huq, Takaaki Ichikawa, Joel Jorgensen, Owen Jungroth, Nishnat Kajla, Ravinder Kajley, Koichi Kawai, Jiro Kishimoto, Ali Madraswala, Tetsuji Manabe, Vikram Mehta, Midori Morooka, Katie Nguyen, Yoko Oikawa, Bharat Pathak, Rod Rozman, Tom Ryan, Andy Sendrowski, William Sheung, Martin Szwarc, Yasuhiro Takashima, Satoru Tamada, Toru Tanzawa
A 172mm2 32Gb MLC NAND flash memory in 34nm CMOS. 236-237 - Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi:
A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD. 238-239 - Seung-Ho Chang, Sok-Kyu Lee, Seong-Je Park, Min-Joong Jung, Jung-Chul Han, In-Soo Wang, Kyu-Hee Lim, Jung-Hwan Lee, Ji-Hwan Kim, Won-Kyung Kang, Tai-Kyu Kang, Hee-Su Byun, Yujong Noh, Lee-Hyun Kwon, Bon-Kwang Koo, Myung Cho, Joong-Seob Yang, Yo-Hwan Koh:
A 48nm 32Gb 8-level NAND flash memory with 5.5MB/s program throughput. 240-241 - Takuya Futatsuyama, Norihiro Fujita, Naoya Tokiwa, Yoshihiko Shindo, Toshiaki Edahiro, Teruhiko Kamei, Hiroaki Nasu, Makoto Iwai, Koji Kato, Yasuyuki Fukuda, Naoaki Kanagawa, Naofumi Abiko, Masahide Matsumoto, Toshihiko Himeno, Toshifumi Hashimoto, Yi-Ching Liu, Hardwell Chibvongodze, Takamitsu Hori, Manabu Sakai, Hong Ding, Yoshiharu Takeuchi, Hitoshi Shiga, Norifumi Kajimura, Yasuyuki Kajitani, Kiyofumi Sakurai, Kosuke Yanagidaira, Toshihiro Suzuki, Yuko Namiki, Tomofumi Fujimura, Man Mui, Hao Nguyen, Seungpil Lee, Alex Mak, Jeffery Lutze, Tooru Maruyama, Toshiharu Watanabe, Takahiko Hara, Shigeo Ohshima:
A 113mm2 32Gb 3b/cell NAND flash memory. 242-243 - Yasufumi Sugimori, Yoshinori Kohama, Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking. 244-245 - Cuong Trinh, Noboru Shibata, Takeshi Nakano, Mikio Ogawa, Jumpei Sato, Yoshikazu Takeyama, Katsuaki Isobe, Binh Le, Farookh Moogat, Nima Mokhlesi, Kenji Kozakai, Patrick Hong, Teruhiko Kamei, Kiyoaki Iwasa, J. Nakai, Takahiro Shimizu, Mitsuaki Honma, Shintaro Sakai, Toshimasa Kawaai, Satoru Hoshi, Jonghak Yuh, Cynthia Hsu, Taiyuan Tseng, Jason Li, Jayson Hu, M. Liu, Shahzad Khalid, J. Chen, Mitsuyuki Watanabe, Hung-Szu Lin, Junhui Yang, K. McKay, Khanh Nguyen, Tuan Pham, Y. Matsuda, K. Nakamura, Kazunori Kanebako, Susumu Yoshikawa, W. Igarashi, Atsushi Inoue, T. Takahashi, Yukio Komatsu, C. Suzuki, Kousuke Kanazawa, Masaaki Higashitani, Seungpil Lee, T. Murai, K. Nguyen, James Lan, Sharon Huynh, Mark Murin, Mark Shlick, Menahem Lasser, Raul Cernea, Mehrdad Mofidi, K. Schuegraf, Khandker Quader:
A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS. 246-247
Digital Wireless and Reconfigurability
- Marian Verhelst
A reconfigurable, 0.13µm CMOS 110pJ/pulse, fully integrated IR-UWB receiver for communication and sub-cm ranging. 250-251 - Patrick P. Mercier
A 0.55V 16Mb/s 1.6mW non-coherent IR-UWB digital baseband with ±1ns synchronization accuracy. 252-253 - J.-M. Wei, C.-N. Chen, K.-T. Chen, C.-F. Kuo, B.-H. Ong, C.-H. Lu, C.-C. Liu, H.-C. Chiou, H.-C. Yeh, J.-H. Shieh, K.-S. Huang, K.-I. Li, M.-J. Wu, M.-H. Li, S.-H. Chou, Soong Lin Chew, W.-L. Lien, W.-G. Yau, W.-Z. Ge, W.-C. Lai, W.-H. Ting, Y.-J. Tsai, Y.-C. Yen, Y.-C. Yeh:
A 110nm RFCMOS GPS SoC with 34mW -165dBm tracking sensitivity. 254-255 - Mahdi Shabany, P. Glenn Gulak:
A 0.13µm CMOS 655Mb/s 4×4 64-QAM K-Best MIMO detector. 256-257 - Pierre Busson, Nitin Chawla, Jérôme Bach, Stéphane Le Tual, Harvinder Singh, Vineet Gupta, Pascal Urard:
A 1GHz digital channel multiplexer for satellite OutDoor Unit based on a 65nm CMOS transceiver. 258-259 - Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS. 260-261
Display and Imager Electronics
- Yong-Joon Jeon, Hyung-Min Lee
A piecewise-linear 10b DAC architecture with drain-current modulation for compact AMLCD driver ICs. 264-265 - Hyung-Min Lee
A 10b column driver with variable-current-control interpolation for mobile active-matrix LCDs. 266-267 - Jong-Ho Park, Satoshi Aoyama, Takashi Watanabe, Tomoyuki Akahori, Tomohiko Kosugi, Keigo Isobe, Yuichi Kaneko, Zheng Liu, Kazuki Muramatsu, Takeshi Matsuyama, Takeshi Kawahito:
A 0.1e- vertical FPN 4.7e- read noise 71dB DR CMOS image sensor with 13b column-parallel single-ended cyclic ADCs. 268-269 - Jae Hyuk Jang, Minho Kwon, Edwin Tjandranegara, Kywro Lee, Byunghoo Jung:
A digital driving technique for an 8b QVGA AMOLED display using ΔΣ modulation. 270-271
High-Speed and mm-Wave Circuits
- Kazuhisa Sunaga, Hideyuki Sugita, Koichi Yamaguchi, Kazumasa Suzuki:
An 18Gb/s duobinary receiver with a CDR-assisted DFE. 274-275 - Kun-Hung Tsai, Shen-Iuan Liu:
A 43.7mW 96GHz PLL in 65nm CMOS. 276-277 - Daeik D. Kim, Jonghae Kim, Choongyeun Cho, Jean-Olivier Plouchart, Mahender Kumar, Woo-Hyeong Lee, Ken Rim:
An array of 4 complementary LC-VCOs with 51.4% W-Band coverage in 32nm SOI CMOS. 278-279 - Hsien-Ku Chen, Hsien-Jui Chen, Da-Chiang Chang, Ying-Zong Juang, Yu-Che Yang, Shey-Shi Lu
A mm-wave CMOS multimode frequency divider. 280-281 - Bo-Yu Lin, Kun-Hung Tsai, Shen-Iuan Liu:
A 128.24-to-137.00GHz injection-locked frequency divider in 65nm CMOS. 282-283
TD: Energy-Aware Sensor Systems
- Martin Flatscher, Markus Dielacher
A robust wireless sensor node for in-tire-pressure monitoring. 286-287 - Yao-Joe Yang, Yu-Jie Huang, Hsin-Hung Liao, Tao Wang, Pen-Li Huang, Chii-Wann Lin, Yao-Hong Wang, Shey-Shi Lu
A release-on-demand wireless CMOS drug delivery SoC based on electrothermal activation technique. 288-289 - Jerald Yoo
A 5.2mW self-configured wearable body sensor network controller and a 12µW 54.9% efficiency wirelessly powered sensor for continuous health monitoring system. 290-291 - Mirko Frank, Matthias Kuhl, Gilbert Erdler, Ingo Freund, Yiannos Manoli, Claas Müller, Holger Reinecke:
An integrated power supply system for low-power 3.3V electronics using on-chip polymer electrolyte membrane (PEM) fuel cells. 292-293 - Stephen O'Driscoll, Ada S. Y. Poon, Teresa H. Meng:
A mm-sized implantable power receiver with adaptive link compensation. 294-295 - Yogesh K. Ramadass, Anantha P. Chandrakasan:
An efficient piezoelectric energy-harvesting interface circuit using a bias-flip rectifier and shared inductor. 296-297 - Nathaniel J. Guilar, Rajeevan Amirtharajah
An energy-aware multiple-input power supply with charge recovery for energy harvesting applications. 298-299 - Inge Doms, Patrick Merken, Robert Mertens, Chris Van Hoof
Integrated capacitive power-management circuit for thermal harvesters with output power 10 to 1000µW. 300-301 - Raimon Casanova, Ángel Dieguez
An optically programmable SoC for an autonomous mm3-sized microrobot. 302-303
Ranging and Gb/s Communication
- Egidio Ragonese
A fully integrated 24GHz UWB radar sensor for automotive applications. 306-307 - Vipul Jain, Fred Tzeng, Lei Zhou, Payam Heydari:
A single-chip dual-band 22-to-29GHz/77-to-81GHz BiCMOS transceiver for automotive radars. 308-309 - Yoichi Kawano, Toshihide Suzuki, Masaru Sato, Tatsuya Hirose, Kazukiyo Joshin:
A 77GHz transceiver in 90nm CMOS. 310-311 - David Lachartre, Benoît Denis
A 1.1nJ/b 802.15.4a-compliant fully integrated UWB transceiver in 0.13µm CMOS. 312-313 - Cristian Marcu, Debopriyo Chowdhury, Chintan Thakkar, Lingkai Kong, Maryam Tabesh, Jung-Dong Park, Yanjie Wang, Bagher Afshar, Abhinav Gupta, Amin Arbabian, Simone Gambini, Reza Zamani, Ali M. Niknejad, Elad Alon:
A 90nm CMOS low-power 60GHz transceiver with integrated baseband circuitry. 314-315 - Jri Lee, Yenlin Huang, Yentso Chen, Hsinchia Lu
A low-power fully integrated 60GHz transceiver system with OOK modulation and on-board antenna assembly. 316-317 - Akio Tanaka
A 2.88Gb/s digital hopping UWB transceiver. 318-319
Analog Techniques
- Rong Wu, Kofi A. A. Makinwa, Johan H. Huijsing:
A chopper current-feedback instrumentation amplifier with a 1mHz 1/ƒ noise corner and an AC-coupled ripple-reduction loop. 322-323 - Michiel A. P. Pertijs, Wilko J. Kindt:
A 140dB-CMRR current-feedback instrumentation amplifier employing ping-pong auto-zeroing and chopping. 324-325 - Yu-Shiang Lin, Dennis Sylvester, David T. Blaauw:
A 150pW program-and-hold timer for ultra-low-power sensor platforms. 326-327 - Bernhard Goll, Horst Zimmermann
A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47µW at 0.6V. 328-329 - Mohamed El-Nozahi, Ahmed Amer, Joselyn Torres, Kamran Entesari, Edgar Sánchez-Sinencio:
A 25mA 0.13µm CMOS LDO regulator with power-supply rejection better than -56dB up to 10MHz using a feedforward ripple-cancellation technique. 330-331 - Anne-Johan Annema
A sub-1V bandgap voltage reference in 32nm FinFET technology. 332-333 - Hideaki Majima, Mototsugu Hamada:
A 90nm CMOS CT BPF for Bluetooth transceivers with DT 1b-switched-resistor cutoff-frequency control. 334-335 - Antonio Liscidini
A 1.25mW 75dB-SFDR CT filter with in-band noise reduction. 336-337
Sensors and MEMS
- Y. William Li, Hasnain Lakdawala, Arijit Raychowdhury, Greg Taylor, Krishnamurthy Soumyanath:
A 1.05V 1.6mW 0.45°C 3σ-resolution ΔΣ-based temperature sensor with parasitic-resistance compensation in 32nm CMOS. 340-341 - André Luiz Aita, Michiel A. P. Pertijs, Kofi A. A. Makinwa, Johan H. Huijsing:
A CMOS smart temperature sensor with a batch-calibrated inaccuracy of ±0.25°C (3σ) from -70°C to 130°C. 342-343 - Lasse Aaltonen, Timo Speeti, Mikko Saukoski, Kari Halonen:
An interface for a 300°/s capacitive 2-axis micro-gyroscope with pseudo-CT readout. 344-345 - Fabio Gozzini, Giorgio Ferrari
An instrument-on-chip for impedance measurements on nanobiosensors with attoFarad resoution. 346-347 - Marco Bennati, Federico Thei, Michele Rossi, Marco Crescentini
20.5 A Sub-pA ΔΣ Current Amplifier for Single-Molecule Nanosensors. 348-349 - Jelena Citakovic, Per F. Hovesten, Gino Rocca, Aart van Halteren, Pirmin Rombach, Lars J. Stenberg, Pietro Andreani, Erik Bruun
A compact CMOS MEMS microphone with 66dB SNR. 350-351 - Gerald Zach, Horst Zimmermann
A 2×32 range-finding sensor array with pixel-inherent suppression of ambient light up to 120klx. 352-353 - Franz X. Hutter, Daniel Brosch, Heinz-Gerd Graf, Wolfram Klingler, Markus Strobel, Joachim N. Burghartz:
A 0.25µm logarithmic CMOS imager for emissivity-compensated thermography. 354-355
1OGb/s-to-40Gb/s Transmitters and Receivers
- Yasushi Amamiya, Shunichi Kaeriyama, Hidemi Noguchi, Zin Yamazaki, Tomoyuki Yamase, Ken'ichi Hosoya, Minoru Okamoto, Shiro Tomari, Hiroshi Yamaguchi, Hiroaki Shoda, Hironobu Ikeda, Shinji Tanaka, Tsugio Takahashi, Risato Ohhira, Arihide Noda, Ken'ichiro Hijioka, Akira Tanabe, Sadao Fujita, Nobuhiro Kawahara:
A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems. 358-359 - Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker:
A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS. 360-361 - Ahmad Yazdi, Michael M. Green:
A 40Gb/s full-rate 2: 1 MUX in 0.18µm CMOS. 362-363 - Afshin Momtaz, Michael M. Green:
An 80mW 40Gb/s 7-Tap T/2-Spaced FFE in 65nm CMOS. 364-365 - Jri Lee, Ke-Chung Wu:
A 20Gb/s full-rate linear CDR circuit with automatic frequency acquisition. 366-367 - John F. Bulzacchelli, Timothy O. Dickson, Zeynep Toprak Deniz, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Sergey V. Rylov, Daniel J. Friedman:
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS. 368-369 - Jun Cao, Bo Zhang, Ullas Singh, Delong Cui, Anand Vasani, Adesh Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Bharath Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz:
21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber. 370-371
PA and Antenna Interface
- Jonathan Roderick, Hossein Hashemi:
A 0.13µm CMOS power amplifier with ultra-wide instantaneous bandwidth for imaging applications. 374-375 - Shouhei Kousai, Ali Hajimiri:
An octave-range watt-level fully integrated CMOS switching power mixer array for linearization and back-off efficiency improvement. 376-377 - Debopriyo Chowdhury, Christopher D. Hull, Ofir B. Degani, Pankaj Goyal, Yanjie Wang, Ali M. Niknejad:
A single-chip highly linear 2.4GHz 30dBm power amplifier in 90nm CMOS. 378-379 - Wei L. Chan, John R. Long, Marco Spirito
A 60GHz-band 1V 11.5dBm power amplifier with 11% PAE in 65nm CMOS. 380-381 - Kuba Raczkowski, Steven Thijs, Walter De Raedt
50-to-67GHz ESD-protected power amplifiers in digital 45nm LP CMOS. 382-383 - Hang Song, Bertan Bakkaloglu
A CMOS adaptive antenna-impedance-tuning IC operating in the 850MHz-to-2GHz band. 384-385 - Mohyee Mikhemar, Hooman Darabi, Asad A. Abidi:
A tunable integrated duplexer with 50dB isolation in 40nm CMOS. 386-387
PLLs and Clocks
- Hiva Hedayati, Bertan Bakkaloglu
A 1MHz-bandwidth type-I ΔΣ fractional-N synthesizer for WiMAX applications. 390-391 - Xiang Gao, Eric A. M. Klumperink, Mounir Bohsali, Bram Nauta
A 2.2GHz 7.6mW sub-sampling PLL with -126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18µm CMOS. 392-393 - Ting-Hsu Chien, Chi-Sheng Lin, Ying-Zong Juang, Chun-Ming Huang, Chin-Long Wey:
An edge-missing compensator for fast-settling wide-locking-range PLLs. 394-395 - Lei Lu, Zhichao Gong, Youchun Liao, Hao Min, Zhangwen Tang:
A 975-to-1960MHz fast-locking fractional-N synthesizer with adaptive bandwidth control and 4/4.5 prescaler for digital TV tuners. 396-397 - Xueyi Yu, Woogeun Rhee
A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation. 398-399 - Chao-Ching Hung, Shen-Iuan Liu:
A leakage-suppression technique for phase-locked systems in 65nm CMOS. 400-401 - Kunil Choe, Olivier D. Bernal, David Nuttman, Minkyu Je:
A precision relaxation oscillator with a self-clocked offset-cancellation scheme for implantable biomedical SoCs. 402-403 - Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho:
An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage. 404-405
Wireless Connectivity
- Vito Giannini
A 2mm2 0.1-to-5GHz SDR receiver in 45nm digital CMOS. 408-409 - Domine Leenaerts, Remco van de Beek, Jos Bergervoet, Harish Kundur, Gerard van der Weide, Ajay Kapoor, Tian Yan Pu, Yu Fang, Yujuan Wang, Biju Joseph Mukkada, Hong Sair Lim, Madhu Kiran, Chun Swee Lim, Sorin Badiu, Alan Chang:
A 65nm CMOS inductorless triple-band-group WiMedia UWB PHY. 410-411 - Andrea Mazzanti, Mohammad B. Vahidfar, Marco Sosio, Francesco Svelto:
A reconfigurable demodulator with 3-to-5GHz agile synthesizer for 9-band WiMedia UWB in 65nm CMOS. 412-413 - Guido Retz, Hyman Shanan, Kenneth Mulvaney, Kenneth O'Mahony, Miguel Chanca, Pat Crowley, Charley Billon, Muhammad Kalimuddin Khan, Philip Quinlan:
A highly integrated low-power 2.4GHz transceiver using a direct-conversion diversity receiver in 0.18µm CMOS for IEEE802.15.4 WPAN. 414-415 - Li Lin, Naratip Wongkomet, David Yu, Chi-Hung Lin, Ming He, Brian Nissim, Steven Lyuee, Paul Yu, Todd Sepke, Shervin Shekarchian, Luns Tee, Paul Muller, Jonathan Tam, Thomas Cho:
A fully integrated 2×2 MIMO dual-band dual- mode direct-conversion CMOS transceiver for WiMAX/WLAN applications. 416-417 - Jacques Christophe Rudell, Pankaj Goyal, Christopher D. Hull, Shmuel Ravid, Adil Kidwai:
A 1.1V 5-to-6GHz reduced-component direct-conversion transmit signal path in 45nm CMOS. 418-419 - Hyman Shanan, Guido Retz, Kenneth Mulvaney, Philip Quinlan:
A 2.4GHz 2Mb/s versatile PLL-based transmitter using digital pre-emphasis and auto calibration in 0.18µm CMOS for WPAN. 420-421 - Kuang-Wei Cheng, Karthik Natarajan, David J. Allstot:
A 7.2mW quadrature GPS receiver in 0.13µm CMOS. 422-423 - Namjun Cho, Joonsung Bae, Sunyoung Kim, Hoi-Jun Yoo:
A 10.8mW body-channel-communication/MICS dual-band transceiver for a unified body-sensor-network controller. 424-425
Medical
- Peng Cong, Nattapon Chaimanonart, Wen H. Ko, Darrin J. Young:
A wireless and batteryless 130mg 300µW 10b implantable blood-pressure-sensing microsystem for real-time genetically engineered mice monitoring. 428-429 - Masoud Roham, Paul A. Garris, Pedram Mohseni:
A wireless IC for time-share chemical and electrical neural recording. 430-431 - Ming Yin, Maysam Ghovanloo:
A flexible clockless 32-ch simultaneous wireless neural recording system with adjustable resolution. 432-433 - Tung-Chien Chen, Kuanfu Chen, Zhi Yang, Kimberly Cockerham, Wentai Liu:
A biomedical multiprocessor SoC for closed-loop neuroprosthetic applications. 434-435 - Byungchul Jang, Peiyan Cao, Aaron Chevalier, Andrew D. Ellington, Arjang Hassibi:
A CMOS fluorescent-based biosensor microarray. 436-437 - Hua Wang, Yan Chen, Arjang Hassibi, Axel Scherer, Ali Hajimiri:
A frequency-shift CMOS magnetic biosensor array with single-bead sensitivity and no external magnet. 438-439
Switched-Mode Techniques
- Kyoung-Sik Seol, Young-Jin Woo, Gyu-Hyeong Cho, Gyu-Ha Cho, Jae-Woo Lee, Sung-il Kim:
Multiple-output step-up/down switching DC-DC converter with vestigial current control. 442-443 - Suhwan Kim, Gabriel A. Rincón-Mora:
Single-inductor dual-input dual-output buck-boost fuel-cell-li-ion charging DC-DC converter supply. 444-445 - Feng Su, Wing-Hung Ki
Digitally assisted quasi-V2 hysteretic buck converter with fixed frequency and without using large-ESR capacitor. 446-447 - Patrick P. Siniscalchi, Richard K. Hester:
A 20W/channel Class-D amplifier with significantly reduced common-mode radiated emissions. 448-449 - Miguel Angel Rojas González, Edgar Sánchez-Sinencio:
Two Class-D audio amplifiers with 89/90% efficiency and 0.02/0.03% THD+N consuming less than 1mW of quiescent power. 450-451 - Marco Berkhout:
A 460W Class-D output stage with adaptive gate drive. 452-453
SRAM and Emerging Memory
- Yih Wang
A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management. 456-457 - Osamu Hirabayashi, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Akira Katayama, Gou Fukano, Yuki Fujimura, Takaaki Nakazato, Yasushi Shizuki, Natsuki Kushiyama, Tomoaki Yabe:
A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver. 458-459 - Anant Singh, Michael Ciraula, Don Weiss, John J. Wuu, Philippe Bauser, Paul de Champs, Hamid Daghighian, David E. Fisch, Philippe Graber, Michel Bron:
A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology. 460-461 - Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Shinsaku Saito, Yuichi Ito, Sadahiko Miura, Yuko Kato, Kaoru Mori, Yasuaki Ozaki, Yosuke Kobayashi, Norikazu Ohshima, Keizo Kinoshita, Tetsuhiro Suzuki, Kiyokazu Nagahara, Nobuyuki Ishiwata, Katsumi Suemitsu, Shunsuke Fukami
A 90nm 12ns 32Mb 2T1MTJ MRAM. 462-463 - Hidehiro Shiga
A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes. 464-465
TD: Directions in Computing and Signaling
- Ian A. Young, Edris Mohammed, Jason T. S. Liao, Alexandra M. Kern, Samuel Palermo, Bruce A. Block, Miriam R. Reshotko, Peter L. D. Chang:
Optical I/O technology for tera-scale computing. 468-469 - Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Tadahiro Kuroda, Masayuki Mizuno:
Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing. 470-471 - Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
A stretchable EMI measurement sheet with 8×8 coil array, 2V organic CMOS decoder, and -70dBm EMI detection circuits in 0.18¼m CMOS. 472-473 - Markus Becherer
Field-coupled nanomagnets for interconnect-free nonvolatile computing. 474-475 - Hiroshi Yoshikawa, Atsuko Kawasaki, Tomoaki Iiduka, Yasushi Nishimura, Kazumasa Tanida, Kazutaka Akiyama, Masahiro Sekiguchi, Mie Matsuo, Satoru Fukuchi, Katsutomu Takahashi:
Chip Scale Camera Module (CSCM) using Through-Silicon-Via (TSV). 476-477 - Takashi Morie, Youngjae Kim:
A subjective-contour generation LSI system with expandable pixel-parallel architecture for vision systems. 478-479 - Kiichi Niitsu
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. 480-481
mm-Wave Circuits
- Munkyo Seo, Basanth Jagannathan, Corrado Carta
A 1.1V 150GHz amplifier with 8dB gain and +6dBm saturated output power in standard digital 65nm CMOS using dummy-prefilled microstrip lines. 484-485 - Dan Sandström, Mikko Varonen
W-band CMOS amplifiers achieving +10dBm saturated output oower and 7.5dB NF. 486-487 - James F. Buckwalter, Joohwa Kim:
A 26dB-gain 100GHz Si/SiGe Cascaded Constructive-Wave Amplifier. 488-489 - Satwik A. Patnaik, Narasimha Lanka, Ramesh Harjani:
A dual-mode architecture for a phased-array receiver based on injection locking in 0.13µm CMOS. 490-491 - Jonathan Borremans, Kuba Raczkowski, Piet Wambacq:
A digitally controlled compact 57-to-66GHz front-end in 45nm digital CMOS. 492-493 - Karen Scheir, Gerd Vandersteen, Yves Rolain, Piet Wambacq:
A 57-to-66GHz quadrature PLL in 45nm digital CMOS. 494-495 - Takahiro Nakamura, Toru Masuda, Katsuyoshi Washio, Hiroshi Kondoh:
A 59GHz push-push VCO with 13.9GHz tuning range using loop-ground transmission line for a full-band 60GHz transceiver. 496-497
Short Course
- Ian Galton:
Low-voltage analog and mixed-signal CMOS circuit design. 502
Forums
- Ken Takeuchi:
SSD memory subsystem innovation. 504 - Boyd Fowler:
Medical image sensors. 505 - Stefan Heinen:
GIRAFE: 4G RF frontends. 506 - Raj Amirtharajah
Ultra-low-voltage-circuit design. 507 - John T. Stonick:
ATAC: High-speed interfaces. 508 - Stefan Rusu:
Multi-domain processors. 509 - Jan Craninckx:
Clock synthesis design. 510 - Reid Harrison:
Integrated neural interfaces. 511
Evening Sessions
- Jacques Christophe Rudell, Ali Hajimiri:
Healthy Radios: Radio & microwave devices for the health sciences. 512 - Farrokh Ayazi:
Is fabless MEMS fabulous? 513 - Ali Sheikholeslami, Robert Payne:
Will ADCs overtake binary frontends in backplane signaling? 514 - Roland Thewes:
Highlights of IEDM 2008. 515 - Jed Hurwitz:
Forewarned is four armed: Classic Analog misteakes to avoid. 516 - David Su, Arya Behzad:
Things all RFIC designers should know (But are afraid to ask). 517 - Raf Roovers:
Interleaving ADC's - exploiting the parallelism. 518 - Anantha P. Chandrakasan:
Next generation energy scavenging systems. 519 - Yiwan Wong, Raney Southerland:
MID - 'Scaled down' PC or 'Souped up'' handheld? 520
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