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SoCC 2008: Newport Beach, CA, USA
- 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings. IEEE 2008, ISBN 978-1-4244-2596-9
Keynotes / Plenary Presentations
- Nick Ilyadis:
"SOC challenges in the terabit networks era". 3 - Alexander D. Peleg:
"Future trends in PC computing and their implications to SoC". 4 - Kamran Eshraghian:
"Surfing the iSoC multitechnology platform: Volumetric growth beyond Moore's law". 5-6
Embedded Systems and Multicore Architectures
- Sharath Jayaprakash, Nihar R. Mahapatra:
Energy-optimal signaling and ordering of bits for area-constrained interconnects. 9-12 - Sung-Kwan Ku, Han-Sam Jung, Ki-Seok Chung:
A unified power measurement and management platform for pipelined MPSoC executions. 13-16 - Kaushal R. Gandhi, Nihar R. Mahapatra:
Partitioned reuse cache for energy-efficient soft-error protection of functional units. 17-20 - Jiangjiang Liu, Nihar R. Mahapatra:
The role of interconnects in the performance scalability of multicore architectures. 21-24
System Level Design
- Yibo Chen, Jin Ouyang, Yuan Xie:
ILP-based scheme for timing variation-aware scheduling and resource binding. 27-30 - Ying Yi, Wei Han, Adam Major, Ahmet T. Erdogan
, Tughrul Arslan:
Exploiting loop-level parallelism on multi-core architectures for the wimax physical layer. 31-34 - Mark Muir, Iain Lindsay, Tughrul Arslan, Ioannis Nousias, Sami Khawam, Mark Milward, Nazish Aslam, Adam Major:
Extensible software emulator for reconfigurable instruction cell based processors. 35-40 - Wei Han, Ying Yi, Mark Muir, Ioannis Nousias, Tughrul Arslan, Ahmet Teyfik Erdogan
MRPSIM: A TLM based simulation tool for MPSOCS targeting dynamically reconfigurable processors. 41-44
Signal Integrity
- Selçuk Köse
Pseudo-random clocking to enhance signal integrity. 47-50 - Mikhail Popovich, Eby G. Friedman:
Nanoscale on-chip decoupling capacitors. 51-54 - Yuejian Wu, Sandy Thomson, Han Sun, Chandra Bontu, Eric Hall:
Built-in functional tests for fast validation of a 40Gbps coherent optical receiver SoC ASIC. 55-58 - Bo Fu, Paul Ampadu:
A multi-wire error correction scheme for reliable and energy efficient SOC links using hamming product codes. 59-62
Network on Chip
- Ying-Cherng Lan, Michael C. Chen, Alan P. Su, Yu Hen Hu, Sao-Jie Chen
Fluidity concept for NoC: A congestion avoidance and relief routing scheme. 65-70 - Qiaoyan Yu, Paul Ampadu:
Configurable error correction for multi-wire errors in switch-to-switch SOC links. 71-74 - Azeez Sanusi, Nan Wang, Magdy A. Bayoumi:
Guaranteeing QoS with the pipelined multi-channel central caching NoC communication architecture. 75-78 - Pavel Ghosh, Arunabha Sen:
Energy minimization using a greedy randomized heuristic for the voltage assignment problem in NoC. 79-84
Posters
- Hermann Kopetz, Christian El Salloum, Bernhard Huber, Roman Obermaisser, Christian Paukovits:
Composability in the time-triggered system-on-chip architecture. 87-90 - Sudhakar Surendran, Rubin A. Parekhji, R. Govindarajan:
A systematic approach to synthesis of verification test-suites for modular SoC designs. 91-96 - Ming-Hung Chang, Li-Pu Chuang, I-Ming Chang, Wei Hwang:
A 300-mV 36-muW multiphase dual digital clock output generator with self-calibration. 97-100 - Ji-Man Park, Sung-Ik Jun:
A resistance deviation-to-time interval converter for resistive sensors. 101-104 - Seth H. Groder, Kenneth W. Hsu:
Design methodolgy for HD Photo compression algorithm targeting a FPGA. 105-108 - Shao-Min Hsu, Yuyu Chang, John Choma Jr.:
Design of low flicker noise active CMOS mixer. 109-112 - Farshad Moradi
65NM sub-threshold 11T-SRAM for ultra low voltage applications. 113-118 - Phillip David Ferguson, Tughrul Arslan, Ahmet T. Erdogan
Evaluation of contrast limited adaptive histogram equalization (CLAHE) enhancement on a FPGA. 119-122 - Tuan Vu Cao, Dag T. Wisland, Tor Sverre Lande
Novel start-up circuit with enhanced power-up characteristic for bandgap references. 123-126 - Iris Hui-Ru Jiang, Shung-Wei Lin, Yen-Ting Yu:
Unification of obstacle-avoiding rectilinear Steiner tree construction. 127-130 - Daisaku Seto, Minoru Watanabe:
Analysis of retention time under multi-configuration on a DORGA. 131-134 - Hanni Bagnordi, Mabo Ito:
Performance evaluation of a FFT using adpative clocking. 135-138 - Farhad Alibeygi Parsan, Ahmad Ayatollahi
A comparator-based switched-capacitor integrator using a new charge control circuit. 139-142 - Ethiopia Nigussie, Juha Plosila
Area efficient delay-insensitive and differential current sensing on-chip interconnect. 143-146 - Basab Datta, Wayne P. Burleson:
Temperature measurement in Content Addressable Memory cells using bias-controlled VCO. 147-150 - Syed Waqar Nabi
A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices. 151-154 - Ramin Shariat-Yazdi, Tad A. Kwasniewski:
A multi-mode sphere detector architecture for WLAN applications. 155-158 - Srivathsan Krishnamohan, Nihar R. Mahapatra:
Slack redistribution in pipelined circuits for enhanced soft-error rate reduction. 159-162 - Khalid Latif, Moazzam Fareed Niazi, Hannu Tenhunen, Tiberiu Seceleanu
Application development flow for on-chip distributed architectures. 163-168 - Md. Mahbub Reja, Kambiz K. Moez, Igor M. Filanovsky:
A novel 0.6V CMOS folded Gilbert-cell mixer for UWB applications. 169-172
Low Power Circuit Design
- Mu-Tien Chang, Po-Tsang Huang, Wei Hwang:
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. 175-178 - Ashok Narasimhan, Ramalingam Sridhar:
A low power and low area active clock deskewing technique for sub-90nm technologies. 179-182 - Jun Zhao, Yong-Bin Kim:
A low power 32 nanometer CMOS digitally controlled oscillator. 183-186 - Yi Xin Su, Jimson Mathew, Jawar Singh, Dhiraj K. Pradhan:
Pseudo parallel architecture for AES with error correction. 187-190
H.264
- Jian Wang, Gang Hua:
Implementing high definition video codec on TI DM6467 SOC. 193-196 - Michelle Brown, Kenneth W. Hsu:
A novel 5.46 mW H.264/AVC video stream parser IC. 197-200 - Michael N. Michael, Kenneth W. Hsu:
A low-power design of quantization for H.264 video coding standard. 201-204 - Chae-Eun Rhee, Jin-Su Jung, Hyuk-Jae Lee:
Speed control for a hardware based H.264/AVC encoder. 205-208
Low Power Design Methodologies
- Jin Ouyang, Yuan Xie:
Power optimization for FinFET-based circuits using genetic algorithms. 211-214 - Wei-Chih Hsieh, Wei Hwang:
In-situ self-aware adaptive power control system with multi-mode power gating network. 215-218 - Dipanjan Sengupta, Resve A. Saleh:
Supply voltage selection in Voltage Island based SoC design. 219-222
Video Processing
- Ricardo Citro, Miguel Guerrero, Jae-Beom Lee, Maria Pantoja:
A multi-standard micro-programmable deblocking filter architecture and its application to VC-1 video decoder. 225-228 - Liang Lu, John V. McCanny, Sakir Sezer:
Multi-standard sub-pixel interpolation architecture for video Motion Estimation. 229-232 - Yu-Yu Lee, Yu-Hsuan Lee, Tsung-Han Tsai:
An efficient lossless embedded compression engine using compacted-FELICS algorithm. 233-236
SRAM Memory Technologies
- Hao-I Yang, Ssu-Yun Lai, Wei Hwang:
Low-power floating bitline 8-T SRAM design with write assistant circuits. 239-242 - Jawar Singh
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. 243-246 - Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi:
Low power 8T SRAM using 32nm independent gate FinFET technology. 247-250 - Jawar Singh
Failure analysis for ultra low power nano-CMOS SRAM under process variations. 251-254
Analog and Mixed-Signal 1
- Fuding Ge, Malay Trivedi, Brent Thomas, William Jiang, Hongjiang Song:
1.5V 0.5mW 2MSPS 10B DAC with rail-to-rail output in 0.13mum CMOS technology. 257-260 - Martin Kosakowski, Reimund Wittmann, Werner Schardein:
Statistical averaging based linearity optimization for resistor string DAC architectures in nanoscale processes. 261-266 - Alexander Lavzin, Mücahit Kozak, Eby G. Friedman:
A higher-order mismatch-shaping method for multi-bit Sigma-Delta Modulators. 267-270 - Sameer Somvanshi, Santhosh Kasavajjala:
A low power sub-1 V CMOS voltage reference. 271-276
Reconfigurable Computing 1
- Mark Hammerquist, Roman L. Lysecky:
Design space exploration for application specific FPGAS in system-on-a-chip designs. 279-282 - Ting Liu, Camel Tanougast
A framework of architectural synthesis for dynamically reconfigurable FPGAs. 283-286 - Samar Yazdani, Joel Cambonie, Bernard Pottier:
Reconfiguralbe multimedia accelerator for mobile systems. 287-290 - Abel G. Silva-Filho, Sidney M. L. Lima:
Energy consumption reduction mechanism by tuning cache configuration usign NIOS II processor. 291-294
Analog and Mixed Signal 2
- Hongjiang Song, Yan Song, Tai-Hua Chen:
VLSI passive switched capacitor signal processing circuits: Circuit architecture, closed form modeling and applications. 297-300 - Minglang Lin, Ahmet T. Erdogan
A novel CMOS exponential approximation circuit. 301-304 - Vijay K. Jain:
3-D Heterogeneous SoC for detecting and filtering infected biological cells. 305-308 - Hongjiang Song:
Novel mixed domain VLSI signal processing circuits for high performance, low power and area penalty SOC signal processing. 309-312
Reconfigurable Computing 2
- Ferney Amaya-Fernandez
Design of a baseband processor for software radio using FPGAs. 315-318 - Xin Zhao, Ahmet T. Erdogan
OFDM symbol timing synchronization system on a Reconfigurable Instruction Cell Array. 319-322 - Cristian E. Onete
Reconfigurable flash A/D converters. 323-326 - Alireza Kaviani, Tao Pi, Declan Kelly:
Programmable all-digital adaptive deskewing and phase shifting. 327-330
Analog and Mixed Signal 3
- Hong-Yi Huang, Li-Wei Huang, Wei-Sheng Tseng, Chih-Yuan Hsu:
A 6-Gbit/s SATA spread-spectrum clock generator using two-stage delta-sigma modulator. 333-336 - Chorng-Sii Hwang, Huan-Chun Li, Hen-Wai Tsao
A spread spectrum clock generator using digital modulation scheme. 337-340 - Hong-Yi Huang, Yi-Jui Tsai, Kung-Liang Ho, Chan-Yu Lin:
All digital time-to-digital converter using single delay-locked loop. 341-344 - Seiede Fateme Ashrafi, Seyed Mojtaba Atarodi
New low voltage, high PSRR, CMOS bandgap voltage reference. 345-348
CAD
- Savithri Sundareswaran, Lucie Nechanicka, Rajendran Panda, Sergey Gavrilov
A timing methodology considering within-die clock skew variations. 351-356 - Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao:
X-clock routing based on pattern matching. 357-360 - Di Phan, Christopher J. Berry, Frank Malgioglio, Alan P. Wagstaff:
An automated design method for chip power distribution. 361-364
Communication and Processing
- Yang Sun, Joseph R. Cavallaro
A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards. 367-370 - Xin Yang, Jun Mu, Sakir Sezer, John V. McCanny, Earl E. Swartzlander Jr.:
High performance IP lookup circuit using DDR SDRAM. 371-374 - Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala
Power/throughput/area efficient PIM-based reconfigurable array for parallel processing. 375-378 - Sangho Yoon, Hanho Lee:
A Discrepancy-Computationless RiBM algorithm and its architecture for BCH decoders. 379-382
Tutorials
- Steve Leibson, Grant Martin:
Design and verification of complex SoC with configurable, extensible processors. 385 - Jason Cong:
A new generation of C-base synthesis tool and domain-specific computing. 386 - Swarup Bhunia, Kaushik Roy:
Low power design under parameter variations. 389-390 - Iain E. Garden Richardson:
Real-time implementation of H.264 Video Coding. 390 - Ad M. G. Peeters, Mark de Wit:
Asynchronous circuit design using Handshake Solutions. 391-392
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