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2020 – today
- 2024
- [j46]Quang Dang Truong
, Phap Duong-Ngoc
Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard. IEEE Access 12: 32395-32407 (2024) - [j45]Rella Mareta, Ardianto Satriawan
A Bootstrapping-Capable Configurable NTT Architecture for Fully Homomorphic Encryption. IEEE Access 12: 52911-52921 (2024) - [j44]Chulwoo Lee, Hanyoung Lee, Ardianto Satriawan
Configurable Arithmetic Core Architecture for RNS-CKKS Homomorphic Encryption. IEEE Access 12: 147220-147234 (2024) - [j43]Ardianto Satriawan
Integer Modular Multiplication With Barrett Reduction and Its Variants for Homomorphic Encryption Applications: A Comprehensive Review and an Empirical Study. IEEE Access 12: 147283-147300 (2024) - [j42]Jiafeng Xie
Hardware Circuits and Systems Design for Post-Quantum Cryptography - A Tutorial Brief. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1670-1676 (2024) - [j41]Hyunseon Kim, Haesung Jung, Ardianto Satriawan
A Configurable ML-KEM/Kyber Key-Encapsulation Hardware Accelerator Architecture. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4678-4682 (2024) - [c58]Rella Mareta, Hanho Lee:
Compact 217 NTT Architecture for Fully Homomorphic Encryption. ISCAS 2024: 1-5 - [c57]Hanyoung Lee, Hanho Lee:
Automorphism Architecture for Bootstrapping Homomorphic Encryption. ISOCC 2024: 159-160 - 2023
- [j40]Phap Duong-Ngoc
Pipelined Key Switching Accelerator Architecture for CKKS-Based Fully Homomorphic Encryption. Sensors 23(10): 4594 (2023) - [j39]Jaehyeok Lee, Phap Duong-Ngoc
Configurable Encryption and Decryption Architectures for CKKS-Based Homomorphic Encryption. Sensors 23(17): 7389 (2023) - [j38]Phap Duong-Ngoc
Area-Efficient Number Theoretic Transform Architecture for Homomorphic Encryption. IEEE Trans. Circuits Syst. I Regul. Pap. 70(3): 1270-1283 (2023) - [j37]Thang Xuan Pham
An Efficient Unified Polynomial Arithmetic Unit for CRYSTALS-Dilithium. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4854-4864 (2023) - [j36]Thang Xuan Pham
Hamming-Distance Trellis Min-Max-Based Architecture for Non-Binary LDPC Decoder. IEEE Trans. Circuits Syst. II Express Briefs 70(7): 2390-2394 (2023) - [j35]Stefanus Kurniawan, Phap Duong-Ngoc
Configurable Memory-Based NTT Architecture for Homomorphic Encryption. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3942-3946 (2023) - [c56]Tuy Tan Nguyen
CKKS-Based Homomorphic Encryption Architecture using Parallel NTT Multiplier. ISCAS 2023: 1-4 - [c55]Chulwoo Lee, Hanyoung Lee, Phap Duong-Ngoc, Hanho Lee:
Twiddle Factor Generator Architecture for Number Theoretic Transform. ISOCC 2023: 209-210 - 2022
- [j34]Phap Duong-Ngoc
Configurable Mixed-Radix Number Theoretic Transform Architecture for Lattice-Based Cryptography. IEEE Access 10: 12732-12741 (2022) - [j33]Tuy Tan Nguyen
Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders. Sensors 22(5): 1792 (2022) - [j32]Thang Xuan Pham
Efficient First Four Minimum Values Finder for NB-LDPC Decoders With Compressed Messages. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1024-1028 (2022) - [c54]Tuy Tan Nguyen
Toward A Real-Time Elliptic Curve Cryptography-Based Facial Security System. APCCAS 2022: 364-367 - [c53]Thang Xuan Pham, Phap Duong-Ngoc, Hanho Lee, Tuy Tan Nguyen
Low-Complexity Architecture of Finding First Four Minimum Values for Non-binary LDPC Decoders. ISOCC 2022: 105-106 - [c52]Phap Duong-Ngoc, Thang Xuan Pham, Hanho Lee, Tuy Tan Nguyen
Flexible GPU-Based Implementation of Number Theoretic Transform for Homomorphic Encryption. ISOCC 2022: 259-260 - 2021
- [j31]Thang Xuan Pham
Minimal-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 216-220 (2021) - [c51]Thang Xuan Pham
High-Efficient Nonbinary LDPC Decoder with Early Layer Decoding Schedule. ISCAS 2021: 1-4 - [c50]Phap Duong-Ngoc
Configurable Butterfly Unit Architecture for NTT/INTT in Homomorphic Encryption. ISOCC 2021: 345-346 - [c49]Tuy Nguyen Tan
Novel Performance Evaluation Approach of AMBA AXI-Based SoC Design. ISOCC 2021: 403-404 - 2020
- [j30]Phap Duong-Ngoc
Efficient NewHope Cryptography Based Facial Security System on a GPU. IEEE Access 8: 108158-108168 (2020) - [c48]Phap Duong-Ngoc
Efficient $k$-Parallel Pipelined NTT Architecture for Post Quantum Cryptography. ISOCC 2020: 212-213 - [c47]Thang Xuan Pham
Efficient Check Node Unit Architecture for Non-binary Quasi-Cyclic LDPC Codes. ISOCC 2020: 216-217
2010 – 2019
- 2019
- [j29]Tuy Nguyen Tan
High-Secure Fingerprint Authentication System Using Ring-LWE Cryptography. IEEE Access 7: 23379-23387 (2019) - [j28]Tram Thi Bao Nguyen, Hanho Lee:
Low-complexity multi-mode multi-way split-row layered LDPC decoder for gigabit wireless communications. Integr. 65: 189-200 (2019) - [j27]Huyen Pham Thi, Hanho Lee, Xuan Nghia Pham:
Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes. Integr. 69: 234-241 (2019) - [c46]Huyen Pham Thi, Cuong Dinh The, Xuan Nghia Pham, Hung Dao Tuan, Hanho Lee:
Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder. APCCAS 2019: 213-216 - 2018
- [j26]Huyen Thi Pham
Basic-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes With High-Order Galois Fields. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 496-507 (2018) - [c45]Huyen Pham Thi, Hanho Lee:
Reduced-Complexity Trellis Min-Max Decoder for Non-Binary Ldpc Codes. ICASSP 2018: 1179-1183 - [c44]Tuy Nguyen Tan
High-Secure Low-Latency Ring-LWE Cryptography Scheme for Biomedical Images Storing and Transmitting. ISCAS 2018: 1-4 - [c43]Tram Thi Bao Nguyen, Hanho Lee:
Efficient Four-way Row-splitting Layered QC-LDPC Decoder Architecture. ISOCC 2018: 210-211 - 2017
- [j25]Huyen Thi Pham, Sabooh Ajaz, Hanho Lee:
High-throughput partial-parallel block-layered decoding architecture for nonbinary LDPC codes. Integr. 59: 52-63 (2017) - [j24]Huyen Thi Pham, Hanho Lee
Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 25(5): 1787-1791 (2017) - [c42]Tuy Nguyen Tan
A delay-efficient ring-LWE cryptography architecture for biometric security. ISCAS 2017: 1-4 - [c41]Seunghun Oh, Hanho Lee:
Parallel architecture for concatenated polar-CRC codes. ISOCC 2017: 173-174 - 2016
- [c40]Huyen Thi Pham, Hanho Lee:
Low latency check node unit architecture for nonbinary LDPC decoding. APCCAS 2016: 400-401 - 2015
- [j23]Sabooh Ajaz, Hanho Lee:
Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications. Integr. 51: 21-36 (2015) - [j22]Chang-Seok Choi, Hanho Lee:
Block-Layered Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes. J. Signal Process. Syst. 78(2): 209-222 (2015) - [c39]Huyen Thi Pham, Sabooh Ajaz, Hanho Lee:
Parallel block-layered nonbinary QC-LDPC decoding on GPU. SiPS 2015: 1-6 - 2014
- [j21]Sabooh Ajaz, Hanho Lee:
An efficient radix-4 Quasi-cyclic shift network for QC-LDPC decoders. IEICE Electron. Express 11(2): 20130837 (2014) - [c38]Sabooh Ajaz, Hanho Lee:
Multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad standard. APCCAS 2014: 153-156 - 2013
- [j20]Taesang Cho
A High-Speed Low-Complexity Modified Radix-25 FFT Processor for High Rate WPAN Applications. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 187-191 (2013) - [j19]Seong-In Hwang, Hanho Lee:
Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1337-1341 (2013) - [c37]Jewong Yeon, Hanho Lee:
High-performance iterative BCH decoder architecture for 100 Gb/s optical communications. ISCAS 2013: 1344-1347 - 2012
- [j18]Jeong-In Park, Hanho Lee:
A High-Speed Low-Complexity Time-Multiplexing Reed-Solomon-Based FEC Architecture for Optical Communications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2424-2429 (2012) - [j17]Ming-Der Shieh, Yin-Tsung Hwang, Hanho Lee, Chirn Chye Boon
Implementations of Signal-Processing Algorithms for OFDM Systems. J. Electr. Comput. Eng. 2012: 687172:1-687172:2 (2012) - [j16]Kihoon Lee, Han-Gil Kang, Jeong-In Park, Hanho Lee:
A High-Speed Low-Complexity Concatenated BCH Decoder Architecture for 100 Gb/s Optical Communications. J. Signal Process. Syst. 66(1): 43-55 (2012) - [c36]Shin-Il Lim, In-Sub Choi, Hanho Lee:
Biochemical sensor interface circuits with differential difference amplifier. APCCAS 2012: 176-179 - [c35]Seong-In Hwang, Hanho Lee, Shin-Il Lim:
A novel method of constructing Quasi-Cyclic RS-LDPC codes for 10GBASE-T Ethernet. ISCAS 2012: 1771-1774 - [c34]Chang-Seok Choi, Hanho Lee, Noriaki Kaneda, Young-Kai Chen:
Concatenated non-binary LDPC and HD-FEC codes for 100Gb/s optical transport systems. ISCAS 2012: 1783-1786 - [c33]Jeong-In Park, Jewong Yeon, Seung-Jun Yang, Hanho Lee:
An ultra high-speed time-multiplexing Reed-Solomon-based FEC architecture. ISOCC 2012: 451-454 - 2011
- [j15]Yong-Kyu Kim, Chang-Seok Choi, Hanho Lee:
Low Complexity Filter Architecture for ATSC Terrestrial Broadcasting DTV Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(3): 937-945 (2011) - [j14]Chang-Seok Choi, Hyo-Jin Ahn, Hanho Lee:
High-Throughput Low-Complexity Four-Parallel Reed-Solomon Decoder Architecture for High-Rate WPAN Systems. IEICE Trans. Commun. 94-B(5): 1332-1338 (2011) - [j13]Kisun Jung, Hanho Lee:
Low-Complexity Multi-Mode Memory-Based FFT Processor for DVB-T2 Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(11): 2376-2383 (2011) - [j12]Sangmin Kim
A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1099-1103 (2011) - [c32]Taesang Cho
A high-speed low-complexity modified radix-25 FFT processor for gigabit WPAN applications. ISCAS 2011: 1259-1262 - [c31]Kyung-Il Baek, Hanho Lee, Chang-Seok Choi, Sangmin Kim
A high-throughput LDPC decoder architecture for high-rate WPAN systems. ISCAS 2011: 1311-1314 - [c30]Jeong-In Park, Hanho Lee, Seongsoo Lee:
An area-efficient truncated inversionless Berlekamp-Massey architecture for Reed-Solomon decoders. ISCAS 2011: 2693-2696 - [c29]Yong-Kyu Kim, Chang-Seok Choi, Hanho Lee, Jin-Gyun Chung:
Low-complexity filter and interpolator design for ATSC DTV systems. ISOCC 2011: 432-435 - 2010
- [j11]Sangho Yoon, Hanho Lee, Kihoon Lee:
High-Speed Two-Parallel Concatenated BCH-Based Super-FEC Architecture for Optical Communications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(4): 769-777 (2010) - [c28]Kisun Jung, Hanho Lee:
Low-cost variable-length FFT processor for DVB-T/H applications. APCCAS 2010: 752-755
2000 – 2009
- 2009
- [c27]Chang-Seok Choi, Hanho Lee:
High-speed low-complexity three-parallel reed-solomon decoder for 6-Gbps mmWave WPAN systems. ECCTD 2009: 515-518 - [c26]Sangho Yoon, Hanho Lee, Kihoon Lee, Chang-Seok Choi, Jongyoon Shin, Jongho Kim, Je-Soo Ko:
Two-parallel concatenated BCH super-FEC architecture for 100-GB/S optical communications. SiPS 2009: 036-039 - 2008
- [j10]Seungbeom Lee, Chang-Seok Choi, Hanho Lee:
Two-parallel Reed-Solomon based FEC architecture for optical communications. IEICE Electron. Express 5(10): 374-380 (2008) - [j9]Seungbeom Lee, Hanho Lee:
A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(3): 830-835 (2008) - [j8]Jeesung Lee, Hanho Lee:
A High-Speed Two-Parallel Radix-24 FFT/IFFT Processor for MB-OFDM UWB Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(4): 1206-1211 (2008) - [c25]Sangmin Kim
Flexible LDPC decoder architecture for high-throughput applications. APCCAS 2008: 45-48 - [c24]Hang Liu, Hanho Lee:
A high performance four-parallel 128/64-point radix-24 FFT/IFFT processor for MIMO-OFDM systems. APCCAS 2008: 834-837 - [c23]Seungbeom Lee, Hanho Lee, Chang-Seok Choi, Jongyoon Shin, Je-Soo Ko:
40-Gb/s two-parallel Reed-Solomon based Forward Error Correction architecture for optical communications. APCCAS 2008: 882-885 - [c22]Sangmin Kim
Adaptive quantization in min-sum based irregular LDPC decoder. ISCAS 2008: 536-539 - [c21]Minhyeok Shin, Hanho Lee:
A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications. ISCAS 2008: 960-963 - [c20]Yong-Je Goo, Hanho Lee:
Two bit-level pipelined viterbi decoder for high-performance UWB applications. ISCAS 2008: 1012-1015 - [c19]Sangho Yoon, Hanho Lee:
A Discrepancy-Computationless RiBM algorithm and its architecture for BCH decoders. SoCC 2008: 379-382 - 2007
- [j7]Cheol-Ho Shin, Sangsung Choi, Hanho Lee, Jeong-Ki Pack:
A Design and Performance of 4-Parallel MB-OFDM UWB Receiver. IEICE Trans. Commun. 90-B(3): 672-675 (2007) - [j6]Chang-Seok Choi, Hanho Lee:
A Self-Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform. IEICE Trans. Inf. Syst. 90-D(12): 1932-1938 (2007) - [c18]Yong-Min Lee
Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications. ARC 2007: 283-292 - [c17]Seungbeom Lee, Hanho Lee, Jongyoon Shin, Je-Soo Ko:
A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders. ISCAS 2007: 901-904 - [c16]Chang-Seok Choi, Hanho Lee:
A Partial Self-Reconfigurable Adaptive FIR Filter System. SiPS 2007: 204-209 - 2006
- [c15]Yeong-Jae Oh, Hanho Lee, Chong Ho Lee:
Dynamic Partial Reconfigurable FIR Filter Design. ARC 2006: 30-35 - [c14]Jeesung Lee, Hanho Lee, Sang-in Cho, Sangsung Choi:
A high-speed, low-complexity radix-24 FFT processor for MB-OFDM UWB systems. ISCAS 2006 - [c13]Yeong-Jae Oh, Hanho Lee, Chong Ho Lee:
A reconfigurable FIR filter design using dynamic partial reconfiguration. ISCAS 2006 - [c12]Hanho Lee, Chang-Seok Choi:
Implementation of a FIR Filter on a Partial Reconfigurable Platform. KES (3) 2006: 108-115 - 2005
- [j5]Hanho Lee:
Power-Aware Scalable Pipelined Booth Multiplier. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(11): 3230-3234 (2005) - [j4]Hanho Lee:
A high-speed low-complexity Reed-Solomon decoder for optical communications. IEEE Trans. Circuits Syst. II Express Briefs 52-II(8): 461-465 (2005) - [c11]Hanho Lee:
An ultra high-speed Reed-Solomon decoder. ISCAS (2) 2005: 1036-1039 - [c10]Hanho Lee:
Reconfigurable Power-Aware Scalable Booth Multiplier. KES (1) 2005: 176-183 - [c9]In Ja Jeon, Phill-Kyu Rhee, Hanho Lee:
An Evolvable Hardware System Under Uneven Environment. KES (2) 2005: 319-326 - 2004
- [j3]Hanho Lee, Gerald E. Sobelman:
VLSI Design Of Digit-Serial FPGA Architecture. J. Circuits Syst. Comput. 13(1): 17-52 (2004) - [c8]Hanho Lee:
A power-aware scalable pipelined Booth multiplier. SoCC 2004: 123-126 - 2003
- [j2]Hanho Lee, Gerald E. Sobelman:
Performance evaluation and optimal design for FPGA-based digit-serial DSP functions. Comput. Electr. Eng. 29(2): 357-377 (2003) - [j1]Hanho Lee:
High-speed VLSI architecture for parallel Reed-Solomon decoder. IEEE Trans. Very Large Scale Integr. Syst. 11(2): 288-294 (2003) - [c7]Hanho Lee:
High-speed VLSI architecture for parallel Reed-Solomon decoder. ISCAS (2) 2003: 320-323 - [c6]Hanho Lee:
An Area-Efficient Euclidean Algorithm Block for Reed-Solomon Decoder. ISVLSI 2003: 209-210 - 2000
- [c5]Hanho Lee, Meng-Lin Yu, Leilei Song:
VLSI design of Reed-Solomon decoder architectures. ISCAS 2000: 705-708
1990 – 1999
- 1999
- [c4]Lijun Gao, Sarvesh Shrivastava, Hanho Lee, Gerald E. Sobelman:
A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor. FCCM 1999: 304-305 - 1998
- [c3]Hanho Lee, Gerald E. Sobelman:
Digit-Serial DSP Library for Optimized FPGA Configuration. FCCM 1998: 322-323 - [c2]Hanho Lee, Sarvesh Shrivastava, Gerald E. Sobelman:
FPGA Logic Block Architecture for Digit-Serial DSP Applications (Abstract). FPGA 1998: 257 - 1997
- [c1]Hanho Lee, Gerald E. Sobelman:
A New Low-Voltage Full Adder Circuit. Great Lakes Symposium on VLSI 1997: 88-
Coauthor Index
Tuy Nguyen Tan
aka: Tuy Tan Nguyen
aka: Tuy Tan Nguyen
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