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Jiafeng Xie
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2020 – today
- 2024
- [j37]Jiafeng Xie
, Wenfeng Zhao
Hardware Circuits and Systems Design for Post-Quantum Cryptography - A Tutorial Brief. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1670-1676 (2024) - [j36]Pengzhou He, Samira Carolina Oliva Madrigal, Çetin Kaya Koç, Tianyou Bao, Jiafeng Xie:
CASA: A Compact and Scalable Accelerator for Approximate Homomorphic Encryption. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024(2): 451-480 (2024) - [j35]Tianyou Bao
AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-Based Lightweight PQC. ACM Trans. Reconfigurable Technol. Syst. 17(2): 29:1-29:23 (2024) - [j34]Tianyou Bao
TINA: TMVP-Initiated Novel Accelerator for Lightweight Ring-LWE-Based PQC. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 870-882 (2024) - [j33]Samuel Coulon
FELIX: FPGA-Based Scalable and Lightweight Accelerator for Large Integer Extended GCD. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1684-1695 (2024) - [c33]Pengzhou He
LAMP: Efficient Implementation of Lightweight Accelerator for Polynomial MultiPlication, From Falcon to RBLWE-ENC. ACM Great Lakes Symposium on VLSI 2024: 210-215 - [c32]Pengzhou He, Tianyou Bao, Çetin Kaya Koç, Jiafeng Xie:
HELP: Highly Efficient and Low-Latency Hardware Accelerator for Integer Polynomial Multiplication. ISVLSI 2024: 355-360 - [i7]Samuel Coulon, Tianyou Bao, Jiafeng Xie:
FELIX (XGCD for FALCON): FPGA-based Scalable and Lightweight Accelerator for Large Integer Extended GCD. IACR Cryptol. ePrint Arch. 2024: 1253 (2024) - 2023
- [j32]Pengzhou He
Hardware-Implemented Lightweight Accelerator for Large Integer Polynomial Multiplication. IEEE Comput. Archit. Lett. 22(1): 57-60 (2023) - [j31]Haobo Yuan
Monocular Road Planar Parallax Estimation. IEEE Trans. Image Process. 32: 3690-3701 (2023) - [j30]Pengzhou He
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography. ACM Trans. Reconfigurable Technol. Syst. 16(3): 45:1-45:23 (2023) - [j29]Pengzhou He
COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 596-600 (2023) - [j28]Yazheng Tu
LEAP: Lightweight and Efficient Accelerator for Sparse Polynomial Multiplication of HQC. IEEE Trans. Very Large Scale Integr. Syst. 31(6): 892-896 (2023) - [j27]Pengzhou He
KINA: Karatsuba Initiated Novel Accelerator for Ring-Binary-LWE (RBLWE)-Based Post-Quantum Cryptography. IEEE Trans. Very Large Scale Integr. Syst. 31(10): 1551-1564 (2023) - [c31]Samuel Coulon, Pengzhou He, Tianyou Bao, Jiafeng Xie:
Efficient Hardware RNS Decomposition for Post-Quantum Signature Scheme Falcon. ACSSC 2023: 19-26 - [c30]Pengzhou He, Tianyou Bao
Efficient Implementation of Ring-Binary-LWE-based Lightweight PQC Accelerator on the FPGA Platform. FCCM 2023: 114-120 - [c29]Tianyou Bao, Pengzhou He, Jiafeng Xie, H. S. Jacinto:
AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-based Lightweight PQC. ICFPT 2023: 6 - [c28]Peng Wang, Jiafeng Xie, Xiye Chen, Guozheng Li, Wei Li:
PasCore: A Chinese Overlapping Relation Extraction Model Based on Global Pointer Annotation Strategy. IJCAI 2023: 5215-5223 - [c27]Pengzhou He, Yazheng Tu, Jiafeng Xie:
LOCS: LOw-Latency and ConStant-Timing Implementation of Fixed-Weight Sampler for HQC. ISCAS 2023: 1-5 - [c26]Pengzhou He, Jiafeng Xie:
Novel Implementation of High-Performance Polynomial Multiplication for Unified KEM Saber based on TMVP Design Strategy. ISQED 2023: 1-8 - [i6]Shaoyu Chen, Yunchi Zhang, Bencheng Liao, Jiafeng Xie, Tianheng Cheng, Wei Sui, Qian Zhang, Chang Huang, Wenyu Liu, Xinggang Wang:
VMA: Divide-and-Conquer Vectorized Map Annotation System for Large-Scale Driving Scene. CoRR abs/2304.09807 (2023) - [i5]Samuel Coulon, Pengzhou He, Tianyou Bao, Jiafeng Xie:
Efficient Hardware RNS Decomposition for Post-Quantum Signature Scheme FALCON. IACR Cryptol. ePrint Arch. 2023: 1427 (2023) - 2022
- [j26]Chiou-Yng Lee
Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor. IEEE Access 10: 7926-7936 (2022) - [j25]Benjamin J. Lucas, Ali Alwan, Marion Murzello, Yazheng Tu, Pengzhou He
Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator. IEEE Comput. Archit. Lett. 21(1): 17-20 (2022) - [j24]Saddam Hussain
Certificateless signature schemes in Industrial Internet of Things: A comparative survey. Comput. Commun. 181: 116-131 (2022) - [j23]Yadi Zhong
AFIA: ATPG-Guided Fault Injection Attack on Secure Logic Locking. J. Electron. Test. 38(5): 527-546 (2022) - [j22]José Luis Imaña
Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography. IEEE Trans. Circuits Syst. I Regul. Pap. 69(8): 3297-3307 (2022) - [j21]Jiafeng Xie
Efficient Hardware Implementation of Finite Field Arithmetic $AB+C$AB+C for Binary Ring-LWE Based Post-Quantum Cryptography. IEEE Trans. Emerg. Top. Comput. 10(2): 1222-1228 (2022) - [c25]Tianyou Bao
Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography. CODES+ISSS 2022: 5-6 - [c24]Pengzhou He, Yazheng Tu, Ayesha Khalid, Máire O'Neill, Jiafeng Xie:
HPMA-NTRU: High-Performance Polynomial Multiplication Accelerator for NTRU. DFT 2022: 1-6 - [c23]Jiafeng Xie, Pengzhou He, Tianyou Bao
Ultra Low-Complexity Implementation of Binary Ring-LWE based Post-Quantum Cryptography on FPGA Platform. FPGA 2022: 156 - [c22]Tianyou Bao
Systolic Acceleration of Polynomial Multiplication for KEM Saber and Binary Ring-LWE Post-Quantum Cryptography. HOST 2022: 157-160 - [c21]Pengzhou He, Tianyou Bao
HPMA-Saber: High-Performance Polynomial Multiplication Accelerator for KEM Saber. ICCD 2022: 525-528 - [c20]Guozheng Li
FastRE: Towards Fast Relation Extraction with Convolutional Encoder and Improved Cascade Binary Tagging Framework. IJCAI 2022: 4201-4208 - [c19]Yazheng Tu, Pengzhou He, Chiou-Yng Lee, Danai Chasaki, Jiafeng Xie:
Hardware Implementation of High-Performance Polynomial Multiplication for KEM Saber. ISCAS 2022: 1160-1164 - [i4]Guozheng Li, Xu Chen, Peng Wang, Jiafeng Xie, Qiqing Luo:
FastRE: Towards Fast Relation Extraction with Convolutional Encoder and Improved Cascade Binary Tagging Framework. CoRR abs/2205.02490 (2022) - [i3]Elizabeth Carter, Pengzhou He, Jiafeng Xie:
High-Performance Polynomial Multiplication Hardware Accelerators for KEM Saber and NTRU. IACR Cryptol. ePrint Arch. 2022: 628 (2022) - 2021
- [j20]Pengzhou He
Novel Low-Complexity Polynomial Multiplication Over Hybrid Fields for Efficient Implementation of Binary Ring-LWE Post-Quantum Cryptography. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(2): 383-394 (2021) - [c18]Xingchen Zhou, Peng Wang, Guozheng Li, Jiafeng Xie, Jiangheng Wu:
Weibo-MEL, Wikidata-MEL and Richpedia-MEL: Multimodal Entity Linking Benchmark Datasets. CCKS 2021: 315-320 - [c17]Jiafeng Xie, Pengzhou He, Wujie Wen:
Efficient Implementation of Finite Field Arithmetic for Binary Ring-LWE Post-Quantum Cryptography Through a Novel Lookup-Table-Like Method. DAC 2021: 1279-1284 - [c16]Jiafeng Xie, Pengzhou He, Chiou-Yng Lee:
CROP: FPGA Implementation of High-Performance Polynomial Multiplication in Saber KEM based on Novel Cyclic-Row Oriented Processing Strategy. ICCD 2021: 130-137 - [c15]Guozheng Li, Peng Wang, Jiafeng Xie, Ruilong Cui, Zhenkai Deng:
FEED: A Chinese Financial Event Extraction Dataset Constructed by Distant Supervision. IJCKG 2021: 45-53 - [i2]Haobo Yuan, Teng Chen, Wei Sui, Jiafeng Xie, Lefei Zhang, Yuan Li, Qian Zhang:
Monocular Road Planar Parallax Estimation. CoRR abs/2111.11089 (2021) - 2020
- [c14]Chiou-Yng Lee, Jiafeng Xie:
Efficient Subquadratic Space Complexity Digit-Serial Multipliers over GF(2m) based on Bivariate Polynomial Basis Representation. ASP-DAC 2020: 253-258 - [c13]Jiafeng Xie, Kanad Basu, Kris Gaj, Ujjwal Guin:
Special Session: The Recent Advance in Hardware Implementation of Post-Quantum Cryptography. VTS 2020: 1-10
2010 – 2019
- 2019
- [j19]Chiou-Yng Lee
Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 203-214 (2019) - [j18]Jeng-Shyang Pan
Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach. IEEE Trans. Very Large Scale Integr. Syst. 27(7): 1614-1622 (2019) - [j17]Jiafeng Xie
Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2119-2130 (2019) - [c12]Jiafeng Xie, Chiou-Yng Lee:
Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity. FPGA 2019: 187 - [c11]Jiafeng Xie, Chiou-Yng Lee:
LSM: Novel Low-Complexity Unified Systolic Multiplier over Binary Extension Field. ACM Great Lakes Symposium on VLSI 2019: 343-346 - [c10]Chiou-Yng Lee, Jiafeng Xie:
High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over GF(2m) based on MSPB. HOST 2019: 21-30 - [c9]Chiou-Yng Lee, Jiafeng Xie:
Efficient Scalable Three Operand Multiplier Over GF(2^m) Based on Novel Decomposition Strategy. ICCD 2019: 29-37 - [c8]Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher:
Low-Complexity Systolic Multiplier for GF(2m) using Toeplitz Matrix-Vector Product Method. ISCAS 2019: 1-5 - [c7]Jiangxin Sun, Jiafeng Xie, Jianfang Hu, Zihang Lin, Jianhuang Lai, Wenjun Zeng
Predicting Future Instance Segmentation with Contextual Pyramid ConvLSTMs. ACM Multimedia 2019: 2043-2051 - 2018
- [j16]Chiou-Yng Lee
Efficient Implementation of Karatsuba Algorithm Based Three-Operand Multiplication Over Binary Extension Field. IEEE Access 6: 38234-38242 (2018) - [j15]Zhenji Hu, Jiafeng Xie
Novel Hybrid-Size Digit-Serial Systolic Multiplier over GF(2m). Symmetry 10(11): 540 (2018) - [j14]Mehran Mozaffari Kermani
Reliable Inversion in GF(28) With Redundant Arithmetic for Secure Error Detection of Cryptographic Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3): 696-704 (2018) - [j13]Qiliang Shao, Zhenji Hu, Shaik Nazeem Basha, Zhiping Zhang, Zhiqiang Wu
Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over GF(2m). IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(8): 2455-2465 (2018) - [j12]Jiafeng Xie
Low Register-Complexity Systolic Digit-Serial Multiplier Over GF(2m) Based on Trinomials. IEEE Trans. Multi Scale Comput. Syst. 4(4): 773-783 (2018) - [c6]Jiafeng Xie, Bing Shuai, Jianfang Hu, Jingyang Lin, Wei-Shi Zheng:
Improving Fast Segmentation With Teacher-Student Learning. BMVC 2018: 205 - [c5]Chiou-Yng Lee, Jiafeng Xie:
Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm. ICCD 2018: 187-194 - [i1]Jiafeng Xie, Bing Shuai, Jianfang Hu, Jingyang Lin, Wei-Shi Zheng:
Improving Fast Segmentation With Teacher-student Learning. CoRR abs/1810.08476 (2018) - 2017
- [j11]Jiafeng Xie
Efficient FPGA Implementation of Low-Complexity Systolic Karatsuba Multiplier Over GF(2m) Based on NIST Polynomials. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(7): 1815-1825 (2017) - [j10]Pingxiuqi Chen, Shaik Nazeem Basha, Mehran Mozaffari Kermani
FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over $GF(2^{m})$ and Their Applications in Trinomial Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 725-734 (2017) - [j9]Qiliang Shao, Zhenji Hu, Shaobo Chen, Pingxiuqi Chen, Jiafeng Xie
Low-Complexity Digit-Level Systolic Gaussian Normal Basis Multiplier. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2817-2827 (2017) - [c4]Xiaojun Zhou, Jiafeng Xie:
Evaluating obfuscation performance of novel algorithm-to-architecture mapping techniques in systolic-array-based circuits. AsianHOST 2017: 127-132 - 2016
- [c3]Mehran Mozaffari Kermani
Error detection reliable architectures of Camellia block cipher applicable to different variants of its substitution boxes. AsianHOST 2016: 1-6 - 2015
- [j8]Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao:
High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(1): 110-119 (2015) - [j7]Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao:
Low-Latency High-Throughput Systolic Multipliers Over GF(2m) for NIST Recommended Pentanomials. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 881-890 (2015) - [j6]Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao:
High-Throughput Digit-Level Systolic Multiplier Over GF(2m) Based on Irreducible Trinomials. IEEE Trans. Circuits Syst. II Express Briefs 62-II(5): 481-485 (2015) - [c2]Dinesh Varma Penumetcha, Jiafeng Xie, Saiyu Ren:
FPGA design space exploration of IDEA cryptography IP core. MWSCAS 2015: 1-4 - 2013
- [j5]Jiafeng Xie, Pramod Kumar Meher, Jianjun He:
Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic. IEEE Trans. Computers 62(6): 1170-1178 (2013) - [j4]Jiafeng Xie, Pramod Kumar Meher, Jianjun He:
Low-Complexity Multiplier for GF(2m) Based on All-One Polynomials. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 168-173 (2013) - [j3]Jiafeng Xie, Jianjun He, Pramod Kumar Meher:
Low Latency Systolic Montgomery Multiplier for Finite Field $GF(2^{m})$ Based on Pentanomials. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 385-389 (2013) - 2012
- [c1]Jiafeng Xie, Pramod Kumar Meher, Jianjun He:
Low-latency area-delay-efficient systolic multiplier over GF(2m) for a wider class of trinomials using parallel register sharing. ISCAS 2012: 89-92 - 2011
- [j2]Jianjun He, Jiafeng Xie:
Hardware Efficient Approach for Memoryless-Based Multiplication and Its Application to FIR Filter. J. Comput. 6(11): 2376-2381 (2011) - 2010
- [j1]Jiafeng Xie, Jianjun He, Guanzheng Tan:
FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures. Microelectron. J. 41(6): 365-370 (2010)
Coauthor Index
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