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ReConFig 2012: Cancun, Quintana Roo, Mexico
- 2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012, Cancun, Mexico, December 5-7, 2012. IEEE 2012, ISBN 978-1-4673-2919-4
- Tannous Frangieh, Peter Athanas:
A design assembly framework for FPGA back-end acceleration. 1-6 - Jaime J. Garnica, Sergio López-Buedo
, Víctor López, Javier Aracil, José María Gómez Hidalgo:
A FPGA-based scalable architecture for URL legal filtering in 100GbE networks. 1-6 - Cuong Pham-Quoc
A heuristic-based communication-aware hardware optimization approach in heterogeneous multicore systems. 1-6 - Razvan Nane
A lightweight speculative and predicative scheme for hardware execution. 1-6 - Hugo A. Andrade, Arkadeb Ghosal, Kaushik Ravindran, Brian L. Evans:
A methodology for the design and deployment of reliable systems on heterogeneous platforms. 1-7 - Mohd Nazrin Md. Isa
A novel efficient FPGA architecture for HMMER acceleration. 1-6 - Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira
A scalable array for Cellular Genetic Algorithms: TSP as case study. 1-6 - Nikolaos Alachiotis
A versatile UDP/IP based PC ↔ FPGA communication platform. 1-6 - Paulo C. Santos, Gabriel L. Nazar, Luigi Carro
Adapting communication for adaptable processors: A multi-axis reconfiguration approach. 1-6 - Michael Schmidt, Dietmar Fey:
Akers's wavefront planner - One of the fastest stencil-based path planners on FPGAs. 1-6 - Vianney Lapotre, Guy Gogniat
An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding. 1-6 - Alex A. Birklykke, Yannick Le Moullec
An automated test framework for experimenting with stochastic behavior in reconfigurable logic. 1-6 - Matthias Pohl, Michael Schaeferling, Gundolf Kiefer, Plamen Petrow, Egmont Woitzel, Frank Papenfuss:
An efficient and scalable architecture for real-time distortion removal and rectification of live camera images. 1-7 - Vincent Mirian, Paul Chow:
An implementation of a directory protocol for a cache coherent system on FPGAs. 1-6 - Frederik Grüll, Michael Kunz, Michael Hausmann, Udo Kebschull:
An implementation of 3D Electron Tomography on FPGAs. 1-5 - Wei He, Andrés Otero
Automatic generation of identical routing pairs for FPGA implemented DPL logic. 1-6 - Oguzhan Erdem, Aydin Carus, Hoang Le:
Compact trie forest: Scalable architecture for IP lookup on FPGAs. 1-6 - Matthias Birk, Matthias Norbert Balzer, Nicole V. Ruiter
Comparison of processing performance and architectural efficiency metrics for FPGAs and GPUs in 3D Ultrasound Computer Tomography. 1-7 - Zoltán Endre Rákossy, Tejas Naphade, Anupam Chattopadhyay:
Design and analysis of layered coarse-grained reconfigurable architecture. 1-6 - David Castells-Rufas
Design of a multi-soft-core based Laser Marking controller. 1-6 - Carsten Tradowsky, Enrique Cordero, Thorsten Deuser, Michael Hübner, Jürgen Becker
Determination of on-chip temperature gradients on reconfigurable hardware. 1-8 - Sen Ma, Miaoqing Huang, David Andrews
Developing application-specific multiprocessor platforms on FPGAs. 1-6 - Andrés Otero
Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems. 1-8 - Venkatasubramanian Viswanathan, Benjamin Nakache, Rabie Ben Atitallah, Maurice Nakache, Jean-Luc Dekeyser:
Dynamic reconfiguration of modular I/O IP cores for avionic applications. 1-6 - Karim M. Abdellatif
Efficient parallel-pipelined GHASH for message authentication. 1-6 - Andrey Bogdanov
Efficient and side-channel resistant authenticated encryption of FPGA bitstreams. 1-6 - Andrey Bogdanov
Efficient reconfigurable hardware architecture for accurately computing success probability and data complexity of linear attacks. 1-6 - Markus Happe
Eight ways to put your FPGA on fire - A systematic study of heat generators. 1-6 - Yukinori Sato
Evaluating reconfigurable dataflow computing using the Himeno benchmark. 1-7 - Rahul R. Sharma, Yamuna Rajasekhar, Ron Sass:
Exploring hardware work queue support for lightweight threads in MPSoCs. 1-6 - Christina Gimmler-Dumont, Philipp Schläfer, Norbert Wehn
FPGA-based rapid prototyping platform for MIMO-BICM design space exploration. 1-7 - Luis Morales-Velazquez
FPGA embedded single-cycle 16-bit microprocessor and tools. 1-6 - Tobias Ziermann, Alexander Butiu, Jürgen Teich, Daniel Ziener
FPGA-based testbed for timing behavior evaluation of the Controller Area Network (CAN). 1-6 - Gilberto Ochoa-Ruiz
Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case study. 1-8 - Andres Upegui, Julien Izui, Gilles Curchod:
Fault mitigation by means of dynamic partial reconfiguration of Virtex-5 FPGAs. 1-6 - Turhan Karadeniz, Lotfi Mhamdi
Hardware design and implementation of a Network-on-Chip based load balancing switch fabric. 1-7 - Mickaël Dardaillon, Cédric Lauradoux, Tanguy Risset:
Hardware implementation of the GPS authentication. 1-6 - Marc Reichenbach
Heterogeneous computer architectures: An image processing pipeline for optical metrology. 1-8 - Victor Silva, Jorge R. Fernandes
A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory. 1-6 - Benedikt Driessen, Tim Güneysu
IPSecco: A lightweight and reconfigurable IPSec core. 1-7 - Andy Caley Data, Kent Gilson:
Isolation of behavior design from system implementation. 1-6 - Ling Liu, Jeremia Bär, Felix Friedrich, Jürg Gutknecht, Shiao-Li Tsao:
A low power configurable SoC for simulating delay-based audio effects. 1-6 - Da Tong, Yi-Hua E. Yang, Viktor K. Prasanna:
A memory efficient IPv6 lookup engine on FPGA. 1-6 - Adrian Alin Lifa, Petru Eles, Zebo Peng:
Minimization of average execution time based on speculative FPGA configuration prefetch. 1-8 - Nashwa Elaraby, Iyad Obeid
A model design of a 2560-channel neural spike detection platform. 1-6 - Laurent Gantel
Module relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow. 1-6 - Daniel Kliem, Sven-Ole Voigt:
A multi-core FPGA-based SoC architecture with domain segregation. 1-7 - Mariem Turki
Multi-FPGA prototyping environment: Large benchmark generation and signals routing. 1-6 - Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A novel physical defects recovery technique for FPGA-IP cores. 1-7 - Johannes Romoth, Dirk Jungewelter, Jens Hagemeyer, Mario Porrmann
Optimizing inter-FPGA communication by automatic channel adaptation. 1-7 - A. D. Santana Gil, Manuel Hernandez Calviño, Francisco Javier Quiles-Latorre, Ezequiel Herruzo Gomez
Optimizing the physical implementation of a reconfigurable cache. 1-6 - Ashraful Alam, Zain-ul-Abdin, Bertil Svensson:
Parallelization of the estimation algorithm of the 3D structure tensor. 1-6 - Robin Bonamy, Daniel Chillet
Power consumption model for partial and dynamic reconfiguration. 1-8 - Tobias Kenter, Henning Schmitz, Christian Plessl
Pragma based parallelization - Trading hardware efficiency for ease of use? 1-8 - Grant Martin:
Keynote 1 - The once and future FPGA: The confluence of configurable processing and reconfigurable technology. 1 - Eric Sivertson:
Keynote 2 - "Reconfigurable Computing and Trust: Foundational technologies to enable trusted reconfigurable platforms". 1 - Bruno de Abreu Silva, Lucas Albers Cuminato, Vanderlei Bonato
Reducing the overall cache miss rate using different cache sizes for Heterogeneous Multi-core Processors. 1-6 - Jeremy Abramson, Pedro C. Diniz:
Resiliency-aware Scheduling for reconfigurable VLIW processors. 1-7 - Uli Kretzschmar, Armando Astarloa
Robustness of different TMR granularities in shared wishbone architectures on SRAM FPGA. 1-6 - Kaveh Aasaraai, Andreas Moshovos:
SPREX: A soft processor with Runahead execution. 1-7 - Dawood Alnajiar, Masanori Hashimoto
Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices. 1-7 - Shweta Jain-Mendon, Ron Sass:
A case study of streaming storage format for sparse matrices. 1-6 - Marc-André Daigneault, Jean-Pierre David:
Synchronized-transfer-level design methodology applied to hardware matrix multiplication. 1-7 - Lubos Gaspar, Viktor Fischer, Tim Güneysu
Two IP protection schemes for multi-FPGA systems. 1-6 - Pedro Cervantes Lozano, Luis Fernando González Pérez, Andrés David García García:
A VLSI architecture for the K-best Sphere-Decoder in MIMO systems. 1-6 - Swapnil Haria, Thilan Ganegedara, Viktor K. Prasanna:
Power-efficient and scalable virtual router architecture on FPGA. 1-7 - Jose Hugo Barron-Zambrano
Versatile FPGA-based locomotion platform for legged robots. 1-6
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