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VLSI-SoC 2017: Abu Dhabi, United Arab Emirates
- 2017 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017. IEEE 2017, ISBN 978-1-5386-2880-5
- Mohammed Ismail:
A self-powered IoT SoC platform for wearable health care. 1-4 - Muhannad S. Bakir:
PhD forum: Heterogeneous interconnection of ICs using stitch-chips. 1-4 - Yervant Zorian:
Keynotes: Robustness challenges in the internet of things. 1-5 - Sukarn Agarwal
, Hemangee K. Kapoor:
Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets. 1-6 - Pedro B. Campos, Nizar Dahir
LeAF: A low-overhead asymmetric frequency controller for NoC router interconnects. 1-6 - Yuan Xue, Abraham Mcllvaine, Chengmo Yang:
Power-aware and cost-efficient state encoding in non-volatile memory based FPGAs. 1-6 - George Michael, Nectarios Efstathiou, Kyriacos Mantis, Theocharis Theocharides, Danilo Pau
Intelligent embedded and real-time ANN-based motor control for multi-rotor unmanned aircraft systems. 1-6 - Stefano Aldegheri, Nicola Bombieri:
Extending OpenVX for model-based design of embedded vision applications. 1-6 - Takashi Nakada, Hiroyuki Yanagihashi
Energy-aware task scheduling for near real-time periodic tasks on heterogeneous multicore processors. 1-6 - Paolo Bernardi
On the in-field testing of spare modules in automotive microprocessors. 1-6 - Brisbane Ovilla-Martinez
Restoration protocol: Lightweight and secur devices authentication based on PUF. 1-6 - R. S. Reshma Raj, Abhijit Das
Implementation and analysis of hotspot mitigation in mesh NoCs by cost-effective deflection routing technique. 1-6 - Ling-Yen Song, Chun Wang, Chien-Nan Jimmy Liu, Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao:
Non-regression approach for the behavioral model generator in mixed-signal system verification. 1-5 - Yonatan Kifle, Hani H. Saleh, Baker Mohammad
A sub-μW bio-potential front end in 65nm CMOS. 1-4 - Hans G. Kerkhoff, Ghazanfar Ali, Jinbo Wan, Ahmed Ibrahim
Applying IJTAG-compatible embedded instruments for lifetime enhancement of analog front-ends of cyber-physical systems. 1-6 - Amir Masoud Gharehbaghi
A new approach for constructing logic functions after ECO. 1-6 - Matthias Thiele, Steve Bigalke, Jens Lienig:
Exploring the use of the finite element method for electromigration analysis in future physical design. 1-6 - Islam Ahmed, Khaled Nouh, Amr Abbas:
Multiple reset domains verification using assertion based verification. 1-6 - David Paul-Pena, Prashanth Krishnamurthy, Ramesh Karri
Process-aware side channel monitoring for embedded control system security. 1-6 - Murugappan Alagappan, Jeyavijayan Rajendran, Milos Doroslovacki, Guru Venkataramani:
DFS covert channels on multi-core platforms. 1-6 - Markus Stefan Wamser, Georg Sigl:
Pushing the limits further: Sub-atomic AES. 1-6 - Daniele Cesarini
Prediction horizon vs. efficiency of optimal dynamic thermal control policies in HPC nodes. 1-6 - Roberto Giorgio Rizzo, Valentino Peluso
Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS. 1-6 - Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano:
Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI. 1-6 - Vivek Nautiyal, Gaurav Singla, Lalit Gupta, Jitendra Dasani, Sagar Dwivedi, Martin Kinkade:
Robust, self-timed power-on reset circuit for low-voltage applications. 1-6 - Shuangxing Zhao, Chenchang Zhan, Guigang Cai:
A 2×VDD-enabled fully-integrated low-dropout regulator with fast transient response. 1-4 - Vikas Rana, Marco Pasotti, F. Desantis:
Single charge-pump generating high positive and negative voltages driving common load. 1-6 - Yuzhe Ma, Xuan Zeng, Bei Yu:
Methodologies for layout decomposition and mask optimization: A systematic review. 1-6 - Youngsoo Song, Jinwook Jung, Youngsoo Shin:
Redundant Via insertion in SADP process with cut merging and optimization. 1-6 - Hoang Anh Du Nguyen, Jintao Yu, Lei Xie, Mottaqiallah Taouil, Said Hamdioui, Dietmar Fey:
Memristive devices for computing: Beyond CMOS and beyond von Neumann. 1-10 - Yanhan Zeng, Xin Zhang, Hong-Zhou Tan
A 86 nA and sub-1 V CMOS voltage reference without resistors and special devices. 1-5 - Xiaopeng Zhong, Amine Bermak
A low-offset dynamic comparator with area-efficient and low-power offset cancellation. 1-6 - Ayman H. Ismail
∑-Δ based force-feedback capacitive micro-machined sensors: Extending the input signal range. 1-6 - Thiago Santos Copetti, Tiago R. Balen, Guilherme Cardoso Medeiros, Letícia Maria Bolzani Poehls:
Analyzing the behavior of FinFET SRAMs with resistive defects. 1-6 - Mini Jayakrishnan, Alan Chang, Tony T. Kim:
Library pruning and sigma corner libraries for power efficient variation tolerant processor pipelines. 1-6 - Binod Kumar, Kanad Basu, Ankit Jindal, Masahiro Fujita, Virendra Singh:
Improving post-silicon error detection with topological selection of trace signals. 1-6 - Joonseop Sim, Mohsen Imani, Yeseong Kim, Tajana Rosing:
Enabling efficient system design using vertical nanowire transistor current mode logic. 1-6 - Juinn-Dar Huang
Defect-aware synthesis for reconfigurable single-electron transistor arrays. 1-6 - Wala Saadeh
A wearable neuro-degenerative diseases detection system based on gait dynamics. 1-6 - Mahesh Kumar Adimulam, Krishna Kumar Movva, Amit Kapoor, M. B. Srinivas:
A low power, programmable bias inverter quantizer (BIQ) flash ADC. 1-6 - Solomon Michael Serunjogi, Kai-Wei Lin, Mahmoud Rasras
Low-jitter, plain vanilla CMOS CDR with half-rate linear PD and half rate frequency detector. 1-6 - Shahzad Muzaffar, Ibrahim M. Elfadel
A pulsed decimal technique for single-channel, dynamic signaling for IoT applications. 1-6 - Masahiro Fujita, Yusuke Kimura, Qinhao Wang:
Template based synthesis for high performance computing. 1-6 - Kyounghoon Kim, Kiyoung Choi:
Synthesis of multi-variate stochastic computing circuits. 1-6 - Abdulhadi Shoufan:
Continuous authentication of UAV flight command data using behaviometrics. 1-6 - Stelvio Cimato
A multiple valued logic approach for the synthesis of garbled circuits. 1-5 - Muhammad Yasin
Evolution of logic locking. 1-6
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