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Xuan Zeng 0001
Person information
- affiliation: Fudan University, State Key Lab of ASIC & System, School of Microelectronics, Shanghai, China
Other persons with the same name
- Xuan Zeng — disambiguation page
- Xuan Zeng 0002
— IRT SystemX, Massy Palaisseau, France (and 1 more)
- Xuan Zeng 0003
- Xuan Zeng 0004
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2020 – today
- 2024
- [j100]Tianchen Gu
BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 417-430 (2024) - [j99]Zhaoting Chen
pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 667-680 (2024) - [j98]Lihao Liu
GNN-Cap: Chip-Scale Interconnect Capacitance Extraction Using Graph Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1206-1217 (2024) - [j97]Xuyang Zhao
ROI-HIT: Region of Interest-Driven High-Dimensional Microarchitecture Design Space Exploration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(11): 4178-4189 (2024) - [j96]Jiarui Bao, Jinxin Zhang, Zhangcheng Huang
Multiagent Based Reinforcement Learning (MA-RL): An Automated Designer for Complex Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(12): 4398-4411 (2024) - [j95]Nanlin Guo
Yield Optimization for Analog Circuits over Multiple Corners via Bayesian Neural Networks: Enhancing Circuit Reliability under Environmental Variation. ACM Trans. Design Autom. Electr. Syst. 29(1): 12:1-12:17 (2024) - [j94]Aidong Zhao
D3PBO: Dynamic Domain Decomposition-based Parallel Bayesian Optimization for Large-scale Analog Circuit Sizing. ACM Trans. Design Autom. Electr. Syst. 29(3): 44:1-44:25 (2024) - [j93]Yiting Liu
Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 810-822 (2024) - [c153]Zihao Chen, Songlei Meng, Fan Yang, Li Shang, Xuan Zeng:
MACRO: Multi-agent Reinforcement Learning-based Cross-layer Optimization of Operational Amplifier. ASPDAC 2024: 423-428 - [c152]Ruiyu Lyu, Yuan Meng, Aidong Zhao, Zhaori Bi, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper). ASPDAC 2024: 671-678 - [c151]Xuyang Zhao, Zhaori Bi, Changhao Yan, Fan Yang, Ye Lu, Dian Zhou, Xuan Zeng:
Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing. ASPDAC 2024: 872-877 - [c150]Zihao Chen
Artisan: Automated Operational Amplifier Design via Domain-specific Large Language Model. DAC 2024: 39:1-39:6 - [c149]Shuyuan Sun
Efficient ILT via Multigrid-Schwartz Method. DAC 2024: 195:1-195:6 - [c148]Tianchen Gu
HiMOSS: A Novel High-dimensional Multi-objective Optimization Method via Adaptive Gradient-Based Subspace Sampling for Analog Circuit Sizing. DAC 2024: 233:1-233:6 - [c147]Handa Sun
EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration. DAC 2024: 284:1-284:6 - [c146]Tianchen Gu
tSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace Sampling. DATE 2024: 1-6 - [c145]Yuan Meng, Ruiyu Lyu, Zhaori Bi, Changhao Yan, Fan Yang, Wenchuang Hu, Dian Zhou, Xuan Zeng:
Circuits Physics Constrained Predictor of Static IR Drop with Limited Data. DATE 2024: 1-2 - [i9]Hongyang Pan, Cunqing Lan, Yiting Liu, Zhiang Wang, Li Shang, Xuan Zeng, Fan Yang, Keren Zhu:
Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement. CoRR abs/2408.07886 (2024) - [i8]Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi, Keren Zhu, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang, Yun Li, Xuan Zeng:
AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis. CoRR abs/2409.08534 (2024) - 2023
- [j92]Cuiyang Ding, Yijing Zhou, Wei Cai
A path integral Monte Carlo (PIMC) method based on Feynman-Kac formula for electrical impedance tomography. J. Comput. Phys. 476: 111862 (2023) - [j91]Biao He
A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 347-359 (2023) - [j90]Zhengqi Gao
Correlated Bayesian Model Fusion: Efficient High-Dimensional Performance Modeling of Analog/RF Integrated Circuits Over Multiple Corners. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 360-370 (2023) - [j89]Chunqiao Li
Unleashing the Power of Graph Spectral Sparsification for Power Grid Analysis via Incomplete Cholesky Factorization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 3053-3066 (2023) - [j88]Jialin Lu
Automatic Op-Amp Generation From Specification to Layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4378-4390 (2023) - [j87]Jiangli Huang
An Analog Circuit Building Block Generator via Nested Multi-Fidelity Modeling. IEEE Trans. Circuits Syst. I Regul. Pap. 70(8): 3280-3293 (2023) - [j86]Jialin Lu
High-Level Topology Synthesis Method for Δ-Σ Modulators via Bi-Level Bayesian Optimization. IEEE Trans. Circuits Syst. II Express Briefs 70(12): 4389-4393 (2023) - [j85]Chunqiao Li
ESPSim: An Efficient Scalable Power Grid Simulator Based on Parallel Algebraic Multigrid. ACM Trans. Design Autom. Electr. Syst. 28(1): 5:1-5:31 (2023) - [j84]Yiting Liu
GraphPlanner: Floorplanning with Graph Neural Network. ACM Trans. Design Autom. Electr. Syst. 28(2): 21:1-21:24 (2023) - [c144]Chengtao An, Chunqiao Li, Xiangqi Li, Yangfeng Su, Fan Yang, Xuan Zeng:
FPDsim: A Structural Simulator For Power Grid Analysis Of Flat Panel Display. DAC 2023: 1-6 - [c143]Shuyuan Sun, Fan Yang, Bei Yu, Li Shang, Xuan Zeng:
Efficient ILT via Multi-level Lithography Simulation. DAC 2023: 1-6 - [c142]Jinxin Zhang, Jiarui Bao, Zhangcheng Huang
Automated Design of Complex Analog Circuits with Multiagent based Reinforcement Learning. DAC 2023: 1-6 - [c141]Aidong Zhao, Xianan Wang, Zixiao Lin, Zhaori Bi
cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis. DAC 2023: 1-6 - [c140]Zihao Chen, Fan Yang, Li Shang, Xuan Zeng:
Automated and Agile Design of Layout Hotspot Detector via Neural Architecture Search. DATE 2023: 1-6 - [c139]Ruiyao Pu, Yiwei Sun, Pei-Hsin Ho, Fan Yang, Li Shang, Xuan Zeng:
Sphinx: A Hybrid Boolean Processor-FPGA Hardware Emulation System. ICCAD 2023: 1-9 - [c138]Zihao Chen, Songlei Meng, Fan Yang, Li Shang, Xuan Zeng:
TOTAL: Topology Optimization of Operational Amplifier via Reinforcement Learning. ISQED 2023: 1-8 - 2022
- [j83]Cuiyang Ding, Changhao Yan
A Parallel Iterative Probabilistic Method for Mixed Problems of Laplace Equations with the Feynman-Kac Formula of Killed Brownian Motions. SIAM J. Sci. Comput. 44(5): 3413- (2022) - [j82]Shuhan Zhang
An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(1): 1-14 (2022) - [j81]Ran Chen
Faster Region-Based Hotspot Detection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 669-680 (2022) - [j80]Zhengqi Gao
Fast Statistical Analysis of Rare Failure Events With Truncated Normal Distribution in High-Dimensional Variation Space. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 789-793 (2022) - [j79]Jun Tao
Correlated Rare Failure Analysis via Asymptotic Probability Evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 813-826 (2022) - [j78]Hao Geng
Hotspot Detection via Attention-Based Deep Layout Metric Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2685-2698 (2022) - [j77]Xiaodong Wang
Analog Circuit Yield Optimization via Freeze-Thaw Bayesian Optimization Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4887-4900 (2022) - [j76]Yifan Wang
Learning From Highly Confident Samples for Automatic Knee Osteoarthritis Severity Assessment: Data From the Osteoarthritis Initiative. IEEE J. Biomed. Health Informatics 26(3): 1239-1250 (2022) - [j75]Yiyang Jiang
Efficient Layout Hotspot Detection via Neural Architecture Search. ACM Trans. Design Autom. Electr. Syst. 27(6): 62:1-62:16 (2022) - [c137]Jingyao Zhao, Changhao Yan, Zhaori Bi, Fan Yang, Xuan Zeng, Dian Zhou:
A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench. ASP-DAC 2022: 86-91 - [c136]Xiaodong Wang, Changhao Yan, Fan Yang, Dian Zhou, Xuan Zeng:
An efficient yield optimization method for analog circuits via gaussian process classification and varying-sigma sampling. DAC 2022: 625-630 - [c135]Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang:
Floorplanning with graph attention. DAC 2022: 1303-1308 - [c134]Jialin Lu, Liangbo Lei, Fan Yang, Li Shang, Xuan Zeng:
Topology Optimization of Operational Amplifier in Continuous Space via Graph Embedding. DATE 2022: 142-147 - [c133]Shuyuan Sun, Yiyang Jiang, Fan Yang, Bei Yu, Xuan Zeng:
Efficient Hotspot Detection via Graph Neural Network. DATE 2022: 1233-1238 - [c132]Longlong Yang, Cuiyang Ding, Changhao Yan, Dian Zhou, Xuan Zeng:
A High-Precision Stochastic Solver for Steady-State Thermal Analysis with Fourier Heat Transfer Robin Boundary Conditions. ICCAD 2022: 50:1-50:9 - [c131]Xu Fu, Changhao Yan, Zhaori Bi, Fan Yang, Dian Zhou, Xuan Zeng:
A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion. ISCAS 2022: 2886-2890 - [c130]Hao Jiang, Fan Yang, Changhao Yan, Xuan Zeng:
SAT-based Scheduling Algorithm for High-level Synthesis Considering Resource Sharing. ISCAS 2022: 3244-3248 - [c129]Shuyuan Sun, Yiyang Jiang, Fan Yang, Xuan Zeng:
Adversarial Sample Generation for Lithography Hotspot Detection. ISCAS 2022: 3503-3506 - [c128]Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces. MLCAD 2022: 27-34 - 2021
- [j74]Junzhe Cai
A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(3): 603-607 (2021) - [j73]Yiyang Jiang
Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(7): 1476-1488 (2021) - [c127]Jiahui Hu, Changhao Yan, Chao Guo, Ronggui Jiang, Dian Zhou, Xuan Zeng:
A Fast Aging-aware Static Timing Analysis Prediction Frame of Digital Integrated Circuits. ASICON 2021: 1-4 - [c126]Yingqi Li, Fan Yang, Changhao Yan, Xuan Zeng:
Efficient High-Level Synthesis of Approximate Computing Circuits via Multi-fidelity Modeling. ASICON 2021: 1-4 - [c125]Yan Wang, Changhao Yan, Dian Zhou, Xuan Zeng:
High-Dimensional Bayesian Optimization for Automated Analog Circuit Design via Add-Graph Structure. ASICON 2021: 1-4 - [c124]Jiangli Huang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization. ASP-DAC 2021: 146-151 - [c123]Zhengqi Gao, Zihao Chen, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng:
Bayesian Inference on Introduced General Region: An Efficient Parametric Yield Estimation Method for Integrated Circuits. ASP-DAC 2021: 892-897 - [c122]Junzhe Cai, Changhao Yan, Yuzhe Ma, Bei Yu, Dian Zhou, Xuan Zeng:
NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis. DAC 2021: 187-192 - [c121]Jialin Lu, Liangbo Lei, Fan Yang, Changhao Yan, Xuan Zeng:
Automated Compensation Scheme Design for Operational Amplifier via Bayesian Optimization. DAC 2021: 517-522 - [c120]Yue Shen, Changhao Yan, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
An Efficient Yield Estimation Method for Layouts of High Dimensional and High Sigma SRAM Arrays. DATE 2021: 1723-1728 - [c119]Hao Geng, Fan Yang, Xuan Zeng, Bei Yu:
When Wafer Failure Pattern Classification Meets Few-shot Learning and Self-Supervised Learning. ICCAD 2021: 1-8 - [c118]Cheng Zeng, Fan Yang, Xuan Zeng:
Accelerate Logic Re-simulation on GPU via Gate/Event Parallelism and State Compression. ICCAD 2021: 1-8 - [c117]Binwu Zhu, Ran Chen, Xinyun Zhang, Fan Yang, Xuan Zeng, Bei Yu, Martin D. F. Wong
Hotspot Detection via Multi-task Learning and Transformer Encoder. ICCAD 2021: 1-8 - [c116]Jiangli Huang, Shuhan Zhang
Bayesian Optimization Approach for Analog Circuit Design Using Multi-Task Gaussian Process. ISCAS 2021: 1-5 - [i7]Shuhan Zhang, Fan Yang, Dian Zhou, Xuan Zeng:
An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis. CoRR abs/2106.14683 (2021) - [i6]Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble. CoRR abs/2106.15412 (2021) - [i5]Shuhan Zhang
LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces. CoRR abs/2109.00617 (2021) - 2020
- [j72]Yiyang Jiang, Fan Yang, Hengliang Zhu, Dian Zhou, Xuan Zeng:
Nonlinear CNN: improving CNNs with quadratic convolutions. Neural Comput. Appl. 32(12): 8507-8516 (2020) - [j71]Zhengqi Gao
Efficient Rare Failure Analysis Over Multiple Corners via Correlated Bayesian Inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2029-2041 (2020) - [j70]Zhengqi Gao
Efficient Parametric Yield Estimation Over Multiple Process Corners via Bayesian Inference Based on Bernoulli Distribution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3144-3148 (2020) - [j69]Fulin Peng, Handi Yu, Jun Tao
Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4971-4984 (2020) - [j68]Yufeng Li, Yan Li, I-Chyn Wey, Deqiang Cheng, Fan Yang, Xuan Zeng, Jie Chen
Improved Low-Power Cost-Effective DCT Implementation Based on Markov Random Field and Stochastic Logic. IEEE Trans. Circuits Syst. Video Technol. 30(10): 3803-3813 (2020) - [j67]Renjian Pan, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li:
Analog/RF Post-silicon Tuning via Bayesian Optimization. ACM Trans. Design Autom. Electr. Syst. 25(1): 7:1-7:17 (2020) - [c115]Shuhan Zhang
Bayesian Methods for the Yield Optimization of Analog and SRAM Circuits. ASP-DAC 2020: 440-445 - [c114]Xiaodong Wang, Tianchen Gu, Changhao Yan, Xiulong Wu, Fan Yang, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits. DAC 2020: 1-6 - [c113]Shuhan Zhang
An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis. DAC 2020: 1-6 - [c112]Biao He, Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling. DATE 2020: 67-72 - [c111]Hao Geng, Haoyu Yang, Lu Zhang, Jin Miao, Fan Yang, Xuan Zeng, Bei Yu:
Hotspot Detection via Attention-based Deep Layout Metric Learning. ICCAD 2020: 16:1-16:8 - [c110]Binbin Liu, Fan Yang, Dian Zhou, Xuan Zeng:
An Efficient Memory Partitioning Approach for Multi-Pattern Data Access in STT-RAM. ISCAS 2020: 1-4 - [c109]Jialin Lu, Shuhan Zhang
A Mixed-Variable Bayesian Optimization Approach for Analog Circuit Synthesis. ISCAS 2020: 1-4 - [c108]Jiahe Shi
Multi-Corner Parametric Yield Estimation via Bayesian Inference on Bernoulli Distribution with Conjugate Prior. ISCAS 2020: 1-4 - [c107]Weijing Wen, Fan Yang, Yangfeng Su, Dian Zhou, Xuan Zeng:
Learning Low-Rank Structured Sparsity in Recurrent Neural Networks. ISCAS 2020: 1-4 - [i4]Zhengqi Gao, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng:
Projection based Active Gaussian Process Regression for Pareto Front Modeling. CoRR abs/2001.07072 (2020)
2010 – 2019
- 2019
- [j66]Changyong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu:
An inverter chain with parallel output nodes for eliminating single-event transient pulse. IEICE Electron. Express 16(4): 20181118 (2019) - [j65]Changyong Liu, Nianlong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu:
A single event upset tolerant latch with parallel nodes. IEICE Electron. Express 16(11): 20190208 (2019) - [j64]Jun Tao
Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(8): 1385-1398 (2019) - [j63]Wensong Li, Fan Yang, Hengliang Zhu, Xuan Zeng, Dian Zhou:
An Efficient Memory Partitioning Approach for Multi-Pattern Data Access via Data Reuse. ACM Trans. Reconfigurable Technol. Syst. 12(1): 1:1-1:22 (2019) - [j62]Chunyu Peng
Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 407-415 (2019) - [j61]Xiang Ge
An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 611-623 (2019) - [c106]Huaidong Gao, Fan Yang, Dian Zhou, Xuan Zeng:
Parallel Global Placement on CPU via Parallel Reduction. ASICON 2019: 1-4 - [c105]Hao Jiang, Yang Fan, Xuan Zeng:
Scheduling Algorithm Based on System of Difference Constraints Using Network Flow. ASICON 2019: 1-4 - [c104]Weijing Wen, Fan Yang, Yangfeng Su, Dian Zhou, Xuan Zeng:
Learning Sparse Patterns in Deep Neural Networks. ASICON 2019: 1-4 - [c103]Shuhan Zhang
An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis. DAC 2019: 64 - [c102]Ran Chen, Wei Zhong, Haoyu Yang, Hao Geng, Xuan Zeng, Bei Yu:
Faster Region-based Hotspot Detection. DAC 2019: 146 - [c101]Yiyang Jiang, Fan Yang, Hengliang Zhu, Bei Yu, Dian Zhou, Xuan Zeng:
Efficient Layout Hotspot Detection via Binarized Residual Neural Network. DAC 2019: 147 - [c100]Xin Wei, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel. DATE 2019: 1040-1045 - [c99]Shuhan Zhang
Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network. DATE 2019: 1463-1468 - [c98]Zhengqi Gao, Jun Tao, Fan Yang, Yangfeng Su, Dian Zhou, Xuan Zeng:
Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural Network. ICCAD 2019: 1-8 - [i3]Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng, Xiangdong Hu:
An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis. CoRR abs/1912.00392 (2019) - [i2]Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network. CoRR abs/1912.00402 (2019) - 2018
- [j60]Qingxue Zhang, Dian Zhou, Xuan Zeng:
A novel single-arm-worn 24 h heart disease monitor empowered by machine intelligence. Biomed. Signal Process. Control. 42: 129-133 (2018) - [j59]Chunyu Peng, Lingyu Kong, Xiulong Wu, Zhiting Lin, Hua Xu, Junning Chen, Xuan Zeng:
Offset voltage suppressed sense amplifier with self-adaptive distribution transformation technique. IEICE Electron. Express 15(10): 20180332 (2018) - [j58]Changyong Liu, Chunyu Peng, Zhiting Lin, Xiulong Wu, Ziyang Chen, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu:
A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination. IEICE Electron. Express 15(15): 20180604 (2018) - [j57]Yan Li, Yufeng Li
Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method. IEEE J. Solid State Circuits 53(8): 2389-2398 (2018) - [j56]Yishi Yang, Hengliang Zhu
Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3): 531-544 (2018) - [j55]Hengliang Zhu
Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 770-781 (2018) - [j54]Mengshuo Wang, Wenlong Lv, Fan Yang, Changhao Yan, Wei Cai, Dian Zhou, Xuan Zeng:
Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 1929-1942 (2018) - [j53]Wenlong Lyu
An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 1954-1967 (2018) - [j52]Jinyuan Zhai, Changhao Yan, Sheng-Guo Wang, Dian Zhou, Hai Zhou, Xuan Zeng:
An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis. ACM Trans. Design Autom. Electr. Syst. 23(3): 36:1-36:23 (2018) - [j51]Hao Zhou
Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1312-1325 (2018) - [j50]Yan Li, Yufeng Li
Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 26(8): 1585-1589 (2018) - [j49]Ye Zhang
Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1613-1626 (2018) - [c97]Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Multi-objective bayesian optimization for analog/RF circuit synthesis. DAC 2018: 11:1-11:6 - [c96]Fulin Peng, Changhao Yan, Chunyang Feng, Jianquan Zheng, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
A general graph based pessimism reduction framework for design optimization of timing closure. DAC 2018: 25:1-25:6 - [c95]Wensong Li, Fan Yang, Hengliang Zhu, Xuan Zeng, Dian Zhou:
An efficient data reuse strategy for multi-pattern data access. ICCAD 2018: 118 - [c94]Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design. ICML 2018: 3312-3320 - [c93]Hao Geng, Haoyu Yang, Bei Yu, Xingquan Li
Sparse VLSI Layout Feature Extraction: A Dictionary Learning Approach. ISVLSI 2018: 488-493 - 2017
- [j48]Qingxue Zhang
A Machine Learning-Empowered System for Long-Term Motion-Tolerant Wearable Monitoring of Blood Pressure and Heart Rate With Ear-ECG/PPG. IEEE Access 5: 10547-10561 (2017) - [j47]Qingxue Zhang
HeartID: A Multiresolution Convolutional Neural Network for ECG-Based Biometric Human Identification in Smart Health Applications. IEEE Access 5: 11805-11816 (2017) - [j46]Guanming Huang, Donesh Gillin, Dian Zhou, Jin Liu, Xuan Zeng, Po-Yu Kuo:
An efficient and robust method to determine the optimal tap coefficients of high speed FIR equalizer. Sci. China Inf. Sci. 60(2): 22401 (2017) - [j45]Qingxue Zhang
A Novel Framework for Motion-Tolerant Instantaneous Heart Rate Estimation by Phase-Domain Multiview Dynamic Time Warping. IEEE Trans. Biomed. Eng. 64(11): 2562-2574 (2017) - [j44]Wei Zeng, Hengliang Zhu
C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance Correlations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(6): 899-912 (2017) - [j43]Fan Yang
Improved Tangent Space-Based Distance Metric for Lithographic Hotspot Classification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(9): 1545-1556 (2017) - [j42]Jincheng Su
Efficient Memory Partitioning for Parallel Data Access in FPGA via Data Reuse. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(10): 1674-1687 (2017) - [j41]Zhaori Bi, Dian Zhou, Sheng-Guo Wang, Xuan Zeng:
Optimization and Quality Estimation of Circuit Design via Random Region Covering Method. ACM Trans. Design Autom. Electr. Syst. 23(1): 1:1-1:25 (2017) - [j40]Yunfeng Yang, Wai-Shing Luk, Hai Zhou, David Z. Pan, Dian Zhou, Changhao Yan, Xuan Zeng:
An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation. ACM Trans. Design Autom. Electr. Syst. 23(1): 11:1-11:27 (2017) - [j39]Mengshuo Wang
High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 806-819 (2017) - [c92]Xiang Ge, Hengliang Zhu, Fan Yang, Lingli Wang, Xuan Zeng:
Parallel sparse LU decomposition using FPGA with an efficient cache architecture. ASICON 2017: 259-262 - [c91]Ye Zhang, Wai-Shing Luk, Fan Yang, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
Network flow based cut redistribution and insertion for advanced 1D layout design. ASP-DAC 2017: 360-365 - [c90]Jiabei Ge, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
An efficient algorithm for stencil planning and optimization in E-beam lithography. ASP-DAC 2017: 366-371 - [c89]Mengshuo Wang, Fan Yang, Changhao Yan, Xuan Zeng, Xiangdong Hu:
Efficient Bayesian Yield Optimization Approach for Analog and SRAM Circuits. DAC 2017: 11:1-11:6 - [c88]Jun Tao, Handi Yu, Dian Zhou, Yangfeng Su, Xuan Zeng, Xin Li:
Correlated Rare Failure Analysis via Asymptotic Probability Evaluation. DAC 2017: 54:1-54:6 - [c87]Wenlong Lv, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits. DATE 2017: 1195-1200 - [c86]Chao Yan, Hengliang Zhu, Dian Zhou, Xuan Zeng:
An efficient leakage-aware thermal simulation approach for 3D-ICs using corrected linearized model and algebraic multigrid. DATE 2017: 1207-1212 - [c85]Handi Yu, Changhao Yan, Xuan Zeng, Xin Li:
Impact of circuit-level non-idealities on vision-based autonomous driving systems. ICCAD 2017: 976-983 - [c84]Fan Yang, Charles C. Chiang, Xuan Zeng, Dian Zhou:
Efficient SVM-based hotspot detection using spectral clustering. ISCAS 2017: 1-4 - [c83]Yunfeng Yang, Fan Yang, Wai-Shing Luk, Changhao Yan, Xuan Zeng, Xiangdong Hu:
Layout decomposition for hybrid E-beam and DSA double patterning lithography. ISCAS 2017: 1-4 - [c82]Ye Zhang, Fan Yang, Dian Zhou, Xuan Zeng, Xiangdong Hu:
A grid-based detailed routing algorithm for advanced 1D process. ISCAS 2017: 1-4 - [c81]Shuhan Zhang
Efficient spectral graph sparsification via Krylov-subspace based spectral perturbation analysis. ISCAS 2017: 1-4 - [c80]Kun Lu, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
A Novel N-Retry Transactional Memory Model for Multi-Thread Programming. ISPA/IUCC 2017: 814-821 - [c79]Qingxue Zhang, Dian Zhou, Xuan Zeng:
Hear the heart: Daily cardiac health monitoring using Ear-ECG and machine learning. UEMCON 2017: 448-451 - [c78]Qingxue Zhang, Dian Zhou, Xuan Zeng:
PulsePrint: Single-arm-ECG biometric human identification using deep learning. UEMCON 2017: 452-456 - [c77]Yuzhe Ma, Xuan Zeng, Bei Yu:
Methodologies for layout decomposition and mask optimization: A systematic review. VLSI-SoC 2017: 1-6 - 2016
- [j38]Minghua Li, Guanming Huang, Xiulong Wu, Liuxi Qian, Xuan Zeng, Dian Zhou:
A yield-enhanced global optimization methodology for analog circuit based on extreme value theory. Sci. China Inf. Sci. 59(8): 082401:1-082401:16 (2016) - [j37]Qicheng Huang, Xiao Li, Chenlei Fang, Fan Yang, Yangfeng Su, Xuan Zeng:
An aggregating based model order reduction method for power grids. Integr. 55: 449-454 (2016) - [j36]Jun Tao, Changhai Liao, Xuan Zeng, Xin Li:
Harvesting Design Knowledge From the Internet: High-Dimensional Performance Tradeoff Modeling for Large-Scale Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(1): 23-36 (2016) - [j35]Changhai Liao, Jun Tao, Xuan Zeng, Yangfeng Su, Dian Zhou, Xin Li:
Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov Tree. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(6): 971-984 (2016) - [j34]Yunfeng Yang, Wai-Shing Luk, David Z. Pan, Hai Zhou, Changhao Yan, Dian Zhou, Xuan Zeng:
Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1532-1545 (2016) - [j33]Changhai Liao, Jun Tao, Handi Yu, Zhangwen Tang, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li:
Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2148-2152 (2016) - [c76]Chenjie Yang, Fan Yang, Xuan Zeng, Dian Zhou:
An efficient trajectory-based algorithm for model order reduction of nonlinear systems via localized projection and global interpolation. ASP-DAC 2016: 551-556 - [c75]Tao Cui, Junqing Chen, Hengliang Zhu, Xuan Zeng:
Algorithms in ParAFEMImp: A Parallel and Wideband Impedance Extraction Program for Complicated 3-D Geometries. BigDataSecurity/HPSC/IDS 2016: 304-309 - [c74]Qicheng Huang, Chenlei Fang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li:
Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits. DAC 2016: 8:1-8:6 - [c73]Chenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li:
Efficient performance modeling of analog integrated circuits via kernel density based sparse regression. DAC 2016: 10:1-10:6 - [c72]Changhai Liao, Jun Tao, Xuan Zeng, Yangfeng Su, Dian Zhou, Xin Li:
Efficient spatial variation modeling via robust dictionary learning. DATE 2016: 121-126 - [c71]Bo Peng, Fan Yang, Changhao Yan, Xuan Zeng, Dian Zhou:
Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data. DATE 2016: 1417-1422 - [c70]Jincheng Su, Fan Yang, Xuan Zeng, Dian Zhou:
Efficient Memory Partitioning for Parallel Data Access via Data Reuse. FPGA 2016: 138-147 - [c69]Handi Yu, Jun Tao, Changhai Liao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li:
Efficient statistical analysis for correlated rare failure events via asymptotic probability approximation. ICCAD 2016: 18 - [c68]Yudong Tao
A novel unified dummy fill insertion framework with SQP-based optimization method. ICCAD 2016: 88 - [c67]Zhelun Yu, Jincheng Su, Fan Yang, Yangfeng Su, Xuan Zeng, Dian Zhou, Weiping Shi:
Fast compressive sensing reconstruction algorithm on FPGA using Orthogonal Matching Pursuit. ISCAS 2016: 249-252 - [c66]Xuan Zeng, Chenlei Fang, Qicheng Huang, Fan Yang, Dian Zhou, Wei Cai, Weiping Shi:
High-speed link verification based on statistical inference. ISCAS 2016: 906-909 - [i1]Junyi Li, Fulin Peng, Fan Yang, Xuan Zeng:
A Memristor Crossbar-Based Computation Scheme with High Precision. CoRR abs/1611.03264 (2016) - 2015
- [j32]Xingbao Zhou, Wai-Shing Luk, Hai Zhou, Fan Yang, Changhao Yan, Xuan Zeng:
Multi-parameter clock skew scheduling. Integr. 48: 129-137 (2015) - [j31]Zhenyu Wu, Changhao Yan, Xuan Zeng, Sheng-Guo Wang:
Rapid estimation of the probability of SRAM failure via adaptive multi-level sliding-window statistical method. Integr. 50: 1-15 (2015) - [j30]Hengliang Zhu, Yuanzhe Wang, Frank Liu, Xin Li, Xuan Zeng, Peter Feldmann:
Efficient Transient Analysis of Power Delivery Network With Clock/Power Gating by Sparse Approximation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(3): 409-421 (2015) - [j29]Xiao Li
MOS Table Models for Fast and Accurate Simulation of Analog and Mixed-Signal Circuits Using Efficient Oscillation-Diminishing Interpolations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(9): 1481-1494 (2015) - [j28]Ye Zhang, Wai-Shing Luk, Yunfeng Yang, Hai Zhou, Changhao Yan, David Z. Pan, Xuan Zeng:
Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography. ACM Trans. Design Autom. Electr. Syst. 21(1): 2:1-2:25 (2015) - [j27]Liuxi Qian, Zhaori Bi, Dian Zhou, Xuan Zeng:
Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2595-2605 (2015) - [c65]Bei Yu, David Z. Pan, Tetsuaki Matsunawa, Xuan Zeng:
Machine learning and pattern matching in physical design. ASP-DAC 2015: 286-293 - [c64]Qicheng Huang, Xiao Li, Fan Yang, Xuan Zeng, Xin Li:
SIPredict: Efficient post-layout waveform prediction via System Identification. ASP-DAC 2015: 460-465 - [c63]Yunfeng Yang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng, Dian Zhou:
Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography. ASP-DAC 2015: 652-657 - [c62]Qicheng Huang, Xiao Li, Chenlei Fang, Fan Yang, Yangfeng Su, Xuan Zeng:
PGMOR: An Efficient Model Order Reduction Method for Power Grids. CAD/Graphics 2015: 242-243 - [c61]Qicheng Huang, Chenlei Fang, Fan Yang, Xuan Zeng, Xin Li:
Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits. DAC 2015: 169:1-169:6 - [c60]Chenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Xin Li, Chenjie Gu:
Efficient bit error rate estimation for high-speed link by Bayesian model fusion. DATE 2015: 1024-1029 - [c59]Minghua Li, Zhaori Bi, Dian Zhou, Xuan Zeng:
Analog circuit performance bound estimation based on extreme value theory. MWSCAS 2015: 1-4 - 2014
- [j26]Xingbao Zhou, Fan Yang, Hai Zhou, Min Gong, Hengliang Zhu, Ye Zhang, Xuan Zeng:
Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(11): 2227-2235 (2014) - [j25]Xiaodong Liu, Gary K. Yeap, Jun Tao, Xuan Zeng:
Integrated Algorithm for 3-D IC Through-Silicon Via Assignment. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 655-666 (2014) - [c58]Chenlei Fang, Fan Yang, Xuan Zeng, Xin Li:
BMF-BD: Bayesian Model Fusion on Bernoulli Distribution for Efficient Yield Estimation of Integrated Circuits. DAC 2014: 29:1-29:6 - [c57]Yuankai Chen, Xuan Zeng, Hai Zhou:
Recovery-based resilient latency-insensitive systems. DATE 2014: 1-6 - 2013
- [j24]Jian Sun, Yinghai Lu, Hai Zhou, Changhao Yan, Xuan Zeng:
Post-routing layer assignment for double patterning with timing critical paths consideration. Integr. 46(2): 153-164 (2013) - [j23]Peng Wu, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng:
An efficient method for gradient-aware dummy fill synthesis. Integr. 46(3): 301-309 (2013) - [j22]Yanling Zhi, Wai-Shing Luk, Hai Zhou, Xuan Zeng:
SmipRef: An efficient method for multi-domain clock skew scheduling. Integr. 46(4): 392-403 (2013) - [j21]Changhao Yan, Wei Cai, Xuan Zeng:
A Parallel Method for Solving Laplace Equations with Dirichlet Data Using Local Boundary Integral Equations and Random Walks. SIAM J. Sci. Comput. 35(4) (2013) - [j20]Guanming Huang, Liuxi Qian, Siwat Saibua, Dian Zhou, Xuan Zeng:
An Efficient Optimization Based Method to Evaluate the DRV of SRAM Cells. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(6): 1511-1520 (2013) - [j19]Wei Li, Dian Zhou, Minghua Li, Binh P. Nguyen, Xuan Zeng:
Near-Field Communication Transceiver System Modeling and Analysis Using SystemC/SystemC-AMS With the Consideration of Noise Issues. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2250-2261 (2013) - [c56]Zhaori Bi, Wei Li, Dian Zhou, Xuan Zeng, Sheng-Guo Wang:
Mixed-signal system verification by SystemC/SystemC-AMS and HSIM-VCS in near field communication tag design. ASICON 2013: 1-4 - [c55]Jun Dong, Hengliang Zhu, Min Xie, Xuan Zeng:
Graph Steiner tree construction and its routing applications. ASICON 2013: 1-4 - [c54]Guanming Huang, Dian Zhou, Xuan Zeng, Shengguo Wang:
A practical method for auto-design and optimization of DC-DC buck converter. ASICON 2013: 1-4 - [c53]Minghua Li, Dian Zhou, Sheng-Guo Wang, Xuan Zeng:
FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp. ASICON 2013: 1-4 - [c52]Liuxi Qian, Dian Zhou, Xuan Zeng, Shengguo Wang:
Oscillator phase noise verification accounting for process variations. ASICON 2013: 1-4 - [c51]Liuxi Qian, Dian Zhou, Xuan Zeng, Fan Yang, Shengguo Wang:
A parallel sparse linear system solver for large-scale circuit simulation based on Schur Complement. ASICON 2013: 1-4 - [c50]Ye Zhang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng:
Layout decomposition with pairwise coloring for multiple patterning lithography. ICCAD 2013: 170-177 - 2012
- [j18]Yanling Zhi, Wai-Shing Luk, Yi Wang, Changhao Yan, Xuan Zeng:
Yield-Driven Clock Skew Scheduling for Arbitrary Distributions of Critical Path Delays. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2172-2181 (2012) - [c49]Yangfeng Su, Fan Yang, Xuan Zeng:
AMOR: an efficient aggregating based model order reduction method for many-terminal interconnect circuits. DAC 2012: 295-300 - [c48]Jing Guo, Fan Yang, Subarna Sinha, Charles C. Chiang, Xuan Zeng:
Improved tangent space based distance metric for accurate lithographic hotspot classification. DAC 2012: 1173-1178 - 2011
- [j17]Zhihua Gui, Fan Yang, Xuan Zeng:
Stochastic Non-homogeneous Arnoldi Method for Analysis of On-Chip Power Grid Networks under Process Variations. IEICE Trans. Electron. 94-C(4): 504-510 (2011) - [j16]Min Gong, Hai Zhou, Li Li, Jun Tao, Xuan Zeng:
Binning Optimization for Transparently-Latched Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 270-283 (2011) - [j15]Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng:
Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 402-415 (2011) - [j14]Zyad Hassan, Nicholas Allec, Fan Yang, Li Shang, Robert P. Dick, Xuan Zeng:
Full-Spectrum Spatial-Temporal Dynamic Thermal Analysis for Nanometer-Scale Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2276-2289 (2011) - [c47]James Williamson, Yinghai Lu, Li Shang, Hai Zhou, Xuan Zeng:
Parallel cross-layer optimization of high-level synthesis and physical design. ASP-DAC 2011: 467-472 - [c46]Li Li, Jian Sun, Yinghai Lu, Hai Zhou, Xuan Zeng:
Low power discrete voltage assignment under clock skew scheduling. ASP-DAC 2011: 515-520 - [c45]Yanling Zhi, Hai Zhou, Xuan Zeng:
A practical method for multi-domain clock skew optimization. ASP-DAC 2011: 521-526 - [c44]Jian Sun, Yinghai Lu, Hai Zhou, Xuan Zeng:
Post-routing layer assignment for double patterning. ASP-DAC 2011: 793-798 - [c43]Xiaodong Liu, Yifan Zhang, Gary K. Yeap, Xuan Zeng:
An integrated algorithm for 3D-IC TSV assignment. DAC 2011: 652-657 - [c42]Yanling Zhi, Wai-Shing Luk, Hai Zhou, Changhao Yan, Hengliang Zhu, Xuan Zeng:
An efficient algorithm for multi-domain clock skew scheduling. DATE 2011: 1364-1369 - [c41]Changhao Yan, Sheng-Guo Wang, Xuan Zeng:
A new method for multiparameter robust stability distribution analysis of linear analog circuits. ICCAD 2011: 420-427 - 2010
- [j13]Jun Tao, Xuan Zeng, Wei Cai, Yangfeng Su, Dian Zhou:
Stochastic Sparse-Grid Collocation Algorithm for Steady-State Analysis of Nonlinear System with Process Variations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(6): 1204-1214 (2010) - [j12]Xuan Zeng, Fan Yang, Yangfeng Su, Wei Cai:
NHAR: A non-homogeneous Arnoldi method for fast simulation of RCL circuits with a large number of ports. Int. J. Circuit Theory Appl. 38(8): 845-865 (2010) - [j11]Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng:
Multicore Parallelization of Min-Cost Flow for CAD Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1546-1557 (2010) - [j10]Ke Zong, Fan Yang, Xuan Zeng:
A Wavelet-Collocation-Based Trajectory Piecewise-Linear Algorithm for Time-Domain Model-Order Reduction of Nonlinear Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(11): 2981-2990 (2010) - [c40]Xiaodong Liu, Yifan Zhang, Gary K. Yeap, Chunlei Chu, Jian Sun, Xuan Zeng:
Global routing and track assignment for flip-chip designs. DAC 2010: 90-93 - [c39]Xiaoda Pan, Fan Yang, Xuan Zeng, Yangfeng Su:
An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits. DATE 2010: 1673-1676 - [c38]Bao Liu, Zhen Cao, Jun Tao, Xuan Zeng, Pushan Tang, H.-S. Philip Wong:
Intel LVS logic as a combinational logic paradigm in CNT technology. NANOARCH 2010: 77-81
2000 – 2009
- 2009
- [j9]Hengliang Zhu, Xuan Zeng, Xu Luo, Wei Cai:
Generalized Stochastic Collocation Method for Variation-Aware Capacitance Extraction of Interconnects Considering Arbitrary Random Probability. IEICE Trans. Electron. 92-C(4): 508-516 (2009) - [j8]Qiang Fu, Wai-Shing Luk, Jun Tao, Changhao Yan, Xuan Zeng:
Characterizing Intra-Die Spatial Correlation Using Spectral Density Fitting Method. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(7): 1652-1659 (2009) - [j7]Qiang Fu, Wai-Shing Luk, Jun Tao, Xuan Zeng, Wei Cai:
Intra-Die Spatial Correlation Extraction with Maximum Likelihood Estimation Method for Multiple Test Chips. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3007-3015 (2009) - [j6]Xu Luo, Fan Yang, Xuan Zeng, Jun Tao, Hengliang Zhu, Wei Cai:
A Modified Nested Sparse Grid Based Adaptive Stochastic Collocation Method for Statistical Static Timing Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3024-3034 (2009) - [c37]Duo Li, Sheldon X.-D. Tan, Gengsheng Chen, Xuan Zeng:
Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method. ASP-DAC 2009: 272-277 - [c36]Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan Yang, Xuan Zeng:
Statistical reliability analysis under process variation and aging effects. DAC 2009: 514-519 - [c35]Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng:
Provably good and practically efficient algorithms for CMP dummy fill. DAC 2009: 539-544 - [c34]Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng:
Multicore parallel min-cost flow algorithm for CAD applications. DAC 2009: 832-837 - [c33]Min Gong, Hai Zhou, Jun Tao, Xuan Zeng:
Binning optimization based on SSTA for transparently-latched circuits. ICCAD 2009: 328-335 - [c32]Tracey Y. Zhou, Dian Zhou, Xuan Zeng:
Incremental Circuit Simulation Analysis for Design Modification and Verification. ISCAS 2009: 2753-2756 - 2008
- [j5]Yi Wang, Xuan Zeng, Jun Tao, Hengliang Zhu, Wei Cai:
Adaptive Stochastic Collocation Method for Parameterized Statistical Timing Analysis with Quadratic Delay Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3465-3473 (2008) - [j4]Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng:
Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1571-1582 (2008) - [c31]Yi Wang, Wai-Shing Luk, Xuan Zeng, Jun Tao, Changhao Yan, Jiarong Tong, Wei Cai, Jia Ni:
Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays. DAC 2008: 223-226 - [c30]Yi Wang, Xuan Zeng, Jun Tao, Hengliang Zhu, Xu Luo, Changhao Yan, Wei Cai:
Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model. ISQED 2008: 62-67 - [c29]Qiang Fu, Wai-Shing Luk, Jun Tao, Changhao Yan, Xuan Zeng:
Characterizing Intra-Die Spatial Correlation Using Spectral Density Method. ISQED 2008: 718-723 - 2007
- [j3]Ming-e Jing, Yue Hao, Dian Zhou, Xuan Zeng:
A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1149-1155 (2007) - [c28]Xuexin Liu, Wai-Shing Luk, Yu Song, Pushan Tang, Xuan Zeng:
Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic. ASP-DAC 2007: 203-208 - [c27]Peng Zhang, Wai-Shing Luk, Yu Song, Jiarong Tong, Pushan Tang, Xuan Zeng:
WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design. ASP-DAC 2007: 209-214 - [c26]Jun Tao, Xuan Zeng, Wei Cai, Yangfeng Su, Dian Zhou, Charles C. Chiang:
Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations. ASP-DAC 2007: 474-479 - [c25]Hengliang Zhu, Xuan Zeng, Wei Cai, Jintao Xue, Dian Zhou:
A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology. DATE 2007: 1514-1519 - [c24]Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng:
Parameterized model order reduction via a two-directional Arnoldi process. ICCAD 2007: 868-873 - [c23]Fan Yang, Xuan Zeng, Yangfeng Su, Dian Zhou:
RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect. ISCAS 2007: 2710-2713 - 2006
- [c22]Hengliang Zhu, Xuan Zeng, Wei Cai, Dian Zhou:
A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations. APCCAS 2006: 1095-1098 - [c21]Xuan Zeng, Lihong Feng, Yangfeng Su, Wei Cai, Dian Zhou, Charles C. Chiang:
Time domain model order reduction by wavelet collocation method. DATE 2006: 21-26 - [c20]Jun Tao, Xuan Zeng, Fan Yang, Yangfeng Su, Lihong Feng, Wei Cai, Dian Zhou, Charles C. Chiang:
A one-shot projection method for interconnects with process variations. ISCAS 2006 - 2005
- [j2]Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng:
Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12): 1915-1924 (2005) - [c19]Bang Liu, Xuan Zeng, Yangfeng Su, Jun Tao, Zhaojun Bai, Charles C. Chiang, Dian Zhou:
Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits. ASP-DAC 2005: 244-249 - [c18]Xuan Zeng, Bang Liu, Jun Tao, Charles C. Chiang, Dian Zhou:
A novel wavelet method for noise analysis of nonlinear circuits. ASP-DAC 2005: 471-476 - [c17]Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng:
Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires. ISCAS (1) 2005: 113-116 - 2004
- [c16]Jian Wang, Jun Tao, Xuan Zeng, Charles C. Chiang, Dian Zhou:
Analog circuit behavioral modeling via wavelet collocation method with auto-companding. ASP-DAC 2004: 45-50 - [c15]Lihong Feng, Xuan Zeng, Charles C. Chiang, Dian Zhou, Qiang Fang:
Direct Nonlinear Order Reduction with Variational Analysis. DATE 2004: 1316-1321 - [c14]Xin Zhou, Dian Zhou, Jin Liu, Ruiming Li, Xuan Zeng, Charles C. Chiang:
Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method. DATE 2004: 1322-1326 - [c13]Yangfeng Su, Jian Wang, Xuan Zeng, Zhaojun Bai, Charles C. Chiang, Dian Zhou:
SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits. ICCAD 2004: 74-79 - [c12]Jian Wang, Xuan Zeng, Wei Cai, Charles C. Chiang, Jiarong Tong, Dian Zhou:
Frequency domain wavelet method with GMRES for large-scale linear circuit simulation. ISCAS (5) 2004: 321-324 - [c11]Lihong Feng, Xuan Zeng, Jiarong Tong, Charles C. Chiang, Dian Zhou:
Two-sided projection method in variational equation model order reduction of nonlinear circuits. ISCAS (4) 2004: 816-819 - 2003
- [j1]Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling, Wei Cai:
Behavioral modeling for analog system-level simulation by wavelet collocation method. IEEE Trans. Circuits Syst. II Express Briefs 50(6): 299-314 (2003) - [c10]Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng:
Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing. ICCAD 2003: 581-587 - [c9]Xuan Zeng, Jun Tao, Yangfeng Su, Wenbing Chen, Dian Zhou:
An error distribution based nonlinear companding method for analog behavioral modeling via wavelet approximation. ISCAS (3) 2003: 168-171 - [c8]Xuan Zeng, Sheng Huang, Yangfeng Su, Dian Zhou:
An efficient Sylvester equation solver for time domain circuit simulation by wavelet collocation method. ISCAS (4) 2003: 664-667 - 2002
- [c7]Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling:
Wavelet method for high-speed clock tree simulation. ISCAS (1) 2002: 177-180 - 2001
- [c6]Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling:
Behavioral Modeling of Analog Circuits by Wavelet Collocation Method. ICCAD 2001: 65-69 - [c5]Xin Li, Bo Hu, Xieting Ling, Xuan Zeng:
A wavelet balance approach for steady-state analysis of nonlinear circuits. ISCAS (3) 2001: 73-76 - [c4]Wei Li, Dian Zhou, Haksu Kim, Xuan Zeng:
Automatic clock tree design with IPs in the system. ISCAS (5) 2001: 387-390 - 2000
- [c3]Xuan Zeng, Mingyuan Li, Wenqing Zhao, Pushan Tang, Dian Zhou:
Parasitic and mismatch modeling for optimal stack generation [in CMOS]. ISCAS 2000: 193-196
1990 – 1999
- 1999
- [c2]Xuan Zeng, J. Guan, Wenqing Zhao, Pushan Tang, Dian Zhou:
A constraint-based placement refinement method for CMOS analog cell layout. ISCAS (6) 1999: 408-411 - [c1]Xuan Zeng, Dian Zhou, Wei Li:
Buffer insertion for clock delay and skew minimization. ISPD 1999: 36-41
Coauthor Index
Sheng-Guo Wang
aka: Shengguo Wang
aka: Shengguo Wang
[j100] [j99] [j97] [j94] [c152] [c151] [c148] [c147] [c146] [c145] [i8] [j92] [j91] [j87] [c141] [j83] [j82] [j77] [c137] [c136] [c132] [c131] [c130] [c128] [j74] [c127] [c126] [c125] [c124] [c122] [c121] [c120] [c116] [i6] [i5] [c114] [c112] [c103] [c100] [c99] [i3] [i2] [j56] [j54] [j53] [j52] [c97] [c96] [c94] [j40] [j39] [c91] [c90] [c89] [c87] [c85] [c83] [c80] [j34] [c71] [c68] [j32] [j31] [j28] [c63] [j24] [j23] [j21] [c50] [j18] [j15] [c42] [c41] [j8] [c35] [c31] [c30] [c29]
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