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Nagarajan Venkateswaran
Person information
- affiliation: Waran Research Foundation (WARF), Chennai, India
Other persons with the same name
- N. Venkateswaran 0001
(aka: Venkateswaran Narasimhan) — SSN College of Engineering, Chennai, India (and 1 more)
- N. Venkateswaran 0003 — Indian Institute of Technology, Centre for Systems and Devices, Chennai, India
- N. Venkateswaran 0004 — Anna University, Chennai, India
- N. Venkateswaran 0005 — Jyothishmathi Institute of Technology and Science, Telangana, India
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2010 – 2019
- 2013
- [c14]Nagarajan Venkateswaran, Kartik Lakshminarasimhan, Akash Sridhar, Prashanth Thinakaran
Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous cores. ISVLSI 2013: 200-205 - 2012
- [c13]Nagarajan Venkateswaran, Rajagopal Hariharan, Vinesh Srinivasan, Ram Srivatsa Kannan, Prashanth Thinakaran
SCOC IP Cores for Custom Built Supercomputing Nodes. ISVLSI 2012: 255-260 - [c12]Nagarajan Venkateswaran, Vinesh Srinivasan, Ram Srivatsa Kannan, Prashanth Thinakaran
Compilation Accelerator on Silicon. ISVLSI 2012: 267-272 - 2010
- [c11]Nagarajan Venkateswaran, Karthikeyan P. Saravanan, Nachiappan Chidambaram Nachiappan
Custom Built Heterogeneous Multi-core Architectures (CUBEMACH): Breaking the conventions. IPDPS Workshops 2010: 1-15
2000 – 2009
- 2009
- [j5]Nagarajan Venkateswaran, Aravind Vasudevan, Balaji Subramaniam, Ravindhiran Mukundrajan, T. P. Ramnath Sai Sagar, Madhavan Manivannan, Sriram Murali, Vinoth Krishnan Elangovan:
Towards modeling and integrated design automation of supercomputing clusters (MIDAS). Comput. Sci. Res. Dev. 24(1-2): 1-10 (2009) - [c10]Nagarajan Venkateswaran, Ravindhiran Mukundrajan, Mrigank Sharma, Badrinarayanan Ravi:
A Non-Uniform Grid Based Ground Plane Model for High Performance Nodes: The Impact of Heterogeneous Cores on Ground Voltage Gradient. ISVLSI 2009: 49-54 - 2008
- [c9]Nagarajan Venkateswaran, Karthik Chandrasekar, Shrikanth Ganapathy:
Design for Testability of Functional Cores in High Performance Node Architectures. DELTA 2008: 302-307 - [c8]Nagarajan Venkateswaran, Vinoth Krishnan Elangovan, Karthik Ganesan, T. R. S. Sagar, S. Aananthakrishanan, S. Ramalingam, Shyamsundar Gopalakrishnan, Madhavan Manivannan, Deepak Srinivasan, Viswanath Krishnamurthy, Karthik Chandrasekar, Viswanath Venkatesan, Balaji Subramaniam, V. Sangkar, Aravind Vasudevan, Shrikanth Ganapathy, Sriram Murali, M. Thyagarajan:
On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system. IPDPS 2008: 1-8 - 2007
- [j4]Nagarajan Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, T. P. Ramnath Sai Sagar, Shyamsundar Gopalakrishnan, Vinoth Krishnan Elangovan, Karthik Chandrasekar, Prem Kumar Ramesh, Viswanath Venkatesan, Arvindakshan Babu, Sudharshan:
Future generation supercomputers I: a paradigm for node architecture. SIGARCH Comput. Archit. News 35(5): 49-60 (2007) - [j3]Nagarajan Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, T. P. Ramnath Sai Sagar, Shyamsundar Gopalakrishnan, Vinoth Krishnan Elangovan, Arvind M, Prem Kumar Ramesh, Karthik Ganesan, Viswanath Krishnamurthy, Sivaramakrishnan:
Future generation supercomputers II: a paradigm for cluster architecture. SIGARCH Comput. Archit. News 35(5): 61-70 (2007) - [c7]Nagarajan Venkateswaran, Arjun Kumeresh, Harish Chandran:
DNA Based Evolutionary Approach for Microprocessor Design Automation. ICANNGA (1) 2007: 11-22 - 2006
- [c6]Arrvindh Shriraman, Nagarajan Venkateswaran, Niranjan Soundararajan:
PASCOM: Power Model for Supercomputers. ARCS 2006: 326-340 - 2005
- [j2]N. Venkateswaran, S. Balaji, V. Sridhar:
Fault tolerant bus architecture for deep submicron based processors. SIGARCH Comput. Archit. News 33(1): 148-155 (2005) - [c5]Nagarajan Venkateswaran, Arrvindh Shriraman, Niranjan Soundararajan:
Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance. IPDPS 2005 - 2004
- [j1]Nagarajan Venkateswaran, Aditya Krishnan, S. Niranjan Kumar, Arrvindh Shriraman, Srinivas Sridharan:
Memory in processor: a novel design paradigm for supercomputing architectures. SIGARCH Comput. Archit. News 32(3): 19-26 (2004) - [c4]N. Venkateswaran, Krishna Bharath:
Frequency Domain Testing of General Purpose Processors at the Instruction Execution Level. DELTA 2004: 15-22 - [c3]N. Venkateswaran, V. Barath Kumar, R. Raghavan, R. Srinivas, S. Subramanian, V. Balaji, Venkataraman Mahalingam, T. L. Rajaprabhu:
Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design. DELTA 2004: 333-340 - 2003
- [c2]N. Venkateswaran, C. Chandramouli:
General Purpose Processor Architecture for Modeling Stochastic Biological Neuronal Assemblies. ICES 2003: 387-397 - [c1]N. Venkateswaran, V. Balaji, Venkataraman Mahalingam, T. L. Rajaprabhu:
Analysis of Bit Transition Count for EDAC Encoded FSM. IOLTS 2003: 166
Coauthor Index
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