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Wei Tang 0010
Person information
- affiliation (PhD 2019): University of Michigan, Department of Electrical Engineering and Computer Science, Ann Arbor, MI, USA
Other persons with the same name
- Wei Tang — disambiguation page
- Wei Tang 0001 — Google Inc, New York, NY, USA (and 2 more)
- Wei Tang 0002
— New Mexico State University, Las Cruces, NM, USA (and 1 more)
- Wei Tang 0003
- Wei Tang 0004
- Wei Tang 0005 — Virginia Tech, Blacksburg, VA, USA
- Wei Tang 0006 — Georgia Institute of Technology, Atlanta, GA, USA
- Wei Tang 0007
- Wei Tang 0008
- Wei Tang 0009
- Wei Tang 0011
- Wei Tang 0012
- Wei Tang 0013
- Wei Tang 0014
- Wei Tang 0015
- Wei Tang 0016
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Journal Articles
- 2024
- [j4]Wei Tang
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration. IEEE J. Solid State Circuits 59(4): 1235-1245 (2024) - 2022
- [j3]Junkang Zhu
VOTA: A Heterogeneous Multicore Visual Object Tracking Accelerator Using Correlation Filters. IEEE J. Solid State Circuits 57(11): 3490-3502 (2022) - 2021
- [j2]Wei Tang
A 0.58-mm2 2.76-Gb/s 79.8-pJ/b 256-QAM Message-Passing Detector for a 128 × 32 Massive MIMO Uplink System. IEEE J. Solid State Circuits 56(6): 1722-1731 (2021) - 2019
- [j1]Wei Tang
A 2.4-mm2 130-mW MMSE-Nonbinary LDPC Iterative Detector Decoder for 4×4 256-QAM MIMO in 65-nm CMOS. IEEE J. Solid State Circuits 54(7): 2070-2080 (2019)
Conference and Workshop Papers
- 2024
- [c11]Vikram Jain
Design Approach for Die-to-Die Interfaces to Enable Energy-Efficient Chiplet Systems. ISLPED 2024: 1-6 - 2023
- [c10]Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Kale, Mark Flannigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang:
Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c9]Teyuh Chou, Wei Tang, Mihai D. Rotaru, Chester Liu, Rahul Dutta, Sharon Lim Pei Siang, David Ho Soon Wee, Surya Bhattacharya, Zhengya Zhang:
NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging. VLSI Technology and Circuits 2022: 208-209 - [c8]Justin M. Correll
An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine. VLSI Technology and Circuits 2022: 264-265 - 2021
- [c7]Sung-Gun Cho, Wei Tang, Chester Liu, Zhengya Zhang
PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA. VLSI Circuits 2021: 1-2 - [c6]Junkang Zhu
VOTA: A 2.45TFLOPS/W Heterogeneous Multi-Core Visual Object Tracking Accelerator Based on Correlation Filters. VLSI Circuits 2021: 1-2 - 2019
- [c5]Teyuh Chou, Wei Tang, Jacob Botimer, Zhengya Zhang
CASCADE: Connecting RRAMs to Extend Analog Dataflow In An End-To-End In-Memory Processing Paradigm. MICRO 2019: 114-125 - 2018
- [c4]Shiming Song, Wei Tang, Thomas Chen, Zhengya Zhang
LEIA: A 2.05mm2 140mW lattice encryption instruction accelerator in 40nm CMOS. CICC 2018: 1-4 - [c3]Wei Tang, Hemanth Prabhu, Liang Liu
A 1.8Gb/s 70.6pJ/b 128×16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI. ISSCC 2018: 224-226 - 2016
- [c2]Wei Tang, Chia-Hsiang Chen, Zhengya Zhang
A 0.58mm2 2.76Gb/s 79.8pJ/b 256-QAM massive MIMO message-passing detector. VLSI Circuits 2016: 1-2 - 2015
- [c1]Chia-Hsiang Chen, Wei Tang, Zhengya Zhang
18.7 A 2.4mm2 130mW MMSE-nonbinary-LDPC iterative detector-decoder for 4×4 256-QAM MIMO in 65nm CMOS. ISSCC 2015: 1-3
Coauthor Index
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last updated on 2024-10-23 20:35 CEST by the dblp team
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